發(fā)布時(shí)間：2018-05-31 10:35

  本文選題：Turbo碼 + 并行譯碼　； 參考：《西南交通大學(xué)》2014年碩士論文

【摘要】：Turbo碼在數(shù)字通信中的重要性眾所周知,其幾乎接近香農(nóng)理論極限的譯碼性能,使得它在各類無(wú)線通信系統(tǒng)中被廣泛應(yīng)用,深空通信、衛(wèi)星通信以及B3G移動(dòng)通信系統(tǒng)等都將Turbo碼作為信道編譯碼方案。為滿足未來(lái)通信系統(tǒng)上百兆信息傳輸速率的需求,設(shè)計(jì)出高速的Turbo譯碼器尤為關(guān)鍵。本文以設(shè)計(jì)高吞吐率的譯碼器為目標(biāo),著重研究了Turbo碼譯碼算法及基于FPGA的硬件實(shí)現(xiàn)技術(shù)。 本文首先介紹了Turbo碼編譯碼原理,然后分析了目前常用的幾種譯碼算法,在此基礎(chǔ)上權(quán)衡譯碼性能以及硬件實(shí)現(xiàn)復(fù)雜度兩方面,選取了復(fù)雜度低并且性能有所改善的Enhanced-Max-Log-MAP譯碼算法作為本文Turbo譯碼器的硬件實(shí)現(xiàn)算法。 在基于FPGA的硬件實(shí)現(xiàn)中,為得到較高的譯碼吞吐率,本文從算法結(jié)構(gòu)以及工作時(shí)鐘頻率兩方面考慮,在算法結(jié)構(gòu)方面,采用分塊并行譯碼、滑窗譯碼、迭代停止判決準(zhǔn)則等高速譯碼方案降低譯碼時(shí)延,并搭建Turbo譯碼器軟件仿真平臺(tái),對(duì)影響譯碼器性能的參數(shù)進(jìn)行仿真,給出Turbo譯碼器的最佳實(shí)現(xiàn)方案。在時(shí)鐘頻率優(yōu)化方面,通過(guò)采用“流水線結(jié)構(gòu)”等技術(shù),提高譯碼器工作時(shí)鐘頻率。 基于上述方案,本文采用Verilog DHL代碼進(jìn)行Turbo譯碼算法設(shè)計(jì),通過(guò)Matlab和Modelsim仿真工具搭建硬件仿真平臺(tái)完成功能仿真驗(yàn)證,在基于Xilinx Virtex-6LX240T FPGA芯片的FT4000系統(tǒng)上完成譯碼器的系統(tǒng)驗(yàn)證,并對(duì)譯碼器的資源消耗和吞吐率性能進(jìn)行分析,最終本文設(shè)計(jì)的譯碼器在碼塊長(zhǎng)度6144bit,并行度8,6次迭代的情況下,譯碼吞吐率滿足100Mbps的性能需求。
[Abstract]:The importance of Turbo code in digital communication is well known, and its decoding performance is close to the limit of Shannon's theory, which makes it widely used in all kinds of wireless communication systems, deep space communication. Satellite communication and B3G mobile communication system take Turbo code as channel coding and decoding scheme. In order to meet the demand of 100 megabit information transmission rate in future communication system, it is very important to design a high speed Turbo decoder. In order to design a decoder with high throughput, this paper focuses on the decoding algorithm of Turbo code and the hardware implementation technology based on FPGA. This paper first introduces the principle of Turbo coding and decoding, then analyzes several decoding algorithms which are commonly used at present. On this basis, the decoding performance and the complexity of hardware implementation are weighed. The Enhanced-Max-Log-MAP decoding algorithm with low complexity and improved performance is selected as the hardware implementation algorithm of the Turbo decoder in this paper. In the hardware implementation based on FPGA, in order to get high throughput, this paper considers the algorithm structure and the working clock frequency. In the aspect of algorithm structure, block parallel decoding and sliding window decoding are adopted. High speed decoding scheme such as iterative stop decision criterion is used to reduce decoding delay. The software simulation platform of Turbo decoder is built to simulate the parameters that affect the performance of the decoder. The optimal implementation scheme of Turbo decoder is given. In the aspect of clock frequency optimization, the clock frequency of decoder is improved by adopting pipeline structure and other techniques. Based on the above scheme, the Turbo decoding algorithm is designed with Verilog DHL code, the hardware simulation platform is built by Matlab and Modelsim simulation tools, and the system verification of the decoder is completed on the FT4000 system based on Xilinx Virtex-6LX240T FPGA chip. The resource consumption and throughput performance of the decoder are analyzed. Finally, the decoding throughput meets the performance requirements of 100Mbps under the condition of block length of 6144 bits and parallel degree of 86 iterations.
【學(xué)位授予單位】：西南交通大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：TN911.2

【參考文獻(xiàn)】

相關(guān)期刊論文 前1條

1 張中培,靳蕃;從相關(guān)性分析Turbo碼交織器的設(shè)計(jì)[J];電子科技大學(xué)學(xué)報(bào);2000年01期

，

本文編號(hào)：1959318