本文選題：功耗攻擊 + 時間交替��； 參考：《國防科學(xué)技術(shù)大學(xué)》2014年碩士論文

【摘要】：功耗攻擊對密碼芯片的安全很具威脅,它通過采集密碼芯片的瞬態(tài)功耗信息從而推算其密鑰,是一種有效的攻擊手段。為了更好的進(jìn)行功耗攻擊,針對密碼芯片工作頻率高,加密部件占總芯片比例較小等特點(diǎn),本文設(shè)計了一套高速高精度的瞬態(tài)功耗采樣系統(tǒng)。時間交替采樣是在保證精度的前提下提高采集速度的一種有效方法,它采用多片相對低速的高精度ADC按照時間交替的方式并行采樣。本文針對時間交替數(shù)據(jù)采集系統(tǒng)通道失配誤差的校正問題,提出了一種頻域時域相結(jié)合的校正方法。該方法采用板載信號源,校準(zhǔn)源時鐘和采集時鐘同源同步,基于FARROW結(jié)構(gòu)的濾波器補(bǔ)償誤差等多種手段,提高了通道失配誤差校正的準(zhǔn)確性。實(shí)測結(jié)果表明:ADC在5GSPS采樣率的情況下,校準(zhǔn)后SNR和SINAD提升達(dá)到30%,SFDR提升達(dá)到60%,說明該方法對誤差有很好的校正效果。時鐘抖動對時間交替采樣系統(tǒng)的精度有較大影響。本文采用時鐘源改進(jìn)、分頻器和帶通濾波器的使用、時鐘鏈路元件數(shù)量縮減等一系列抑制抖動的方法,設(shè)計實(shí)現(xiàn)了一個超低抖動的時鐘產(chǎn)生電路。實(shí)測結(jié)果表明:該電路產(chǎn)生2.5GHz時鐘時,噪聲抖動僅有89.0fs RMS,滿足了時間交替數(shù)據(jù)采集系統(tǒng)的需求。以前述技術(shù)為基礎(chǔ),本項(xiàng)目組設(shè)計并實(shí)現(xiàn)了一套基于時間交替的數(shù)據(jù)采集系統(tǒng),它由模擬信號輸入、時鐘產(chǎn)生分配、電源管理、模數(shù)轉(zhuǎn)換、數(shù)據(jù)接收緩存和數(shù)據(jù)處理上報六個子模塊組成,對整個系統(tǒng)性能的實(shí)測結(jié)果表明:該系統(tǒng)在達(dá)到5GSPS采樣率的同時,采樣精度達(dá)到8位以上。
[Abstract]:Power attack is a threat to the security of cipher chip. It is an effective attack method by collecting the transient power information of cipher chip and calculating its key. In order to attack the power consumption better, a high speed and high precision transient power sampling system is designed to solve the problem of high frequency of cipher chip and small proportion of encryption components. The time alternating sampling is an effective method to improve the acquisition speed under the premise of ensuring the precision. It adopts the multi-chip relatively low speed high precision ADC to sample in parallel according to the time alternating mode. In order to correct the channel mismatch error of time alternating data acquisition system, a frequency domain combined correction method is proposed in this paper. In this method, the accuracy of channel mismatch correction is improved by means of on-board signal source, calibrating source clock and collecting clock homologous synchronization, filter compensation error based on FARROW structure and so on. The measured results show that under the 5GSPS sampling rate, the SNR and SINAD elevations after calibration can reach 30% and 60% respectively, which shows that the proposed method has a good correction effect on the errors. Clock jitter has great influence on the precision of time alternating sampling system. In this paper an ultra-low jitter clock generation circuit is designed and implemented by a series of methods such as clock source improvement the use of frequency divider and bandpass filter and the reduction of the number of clock link elements. The experimental results show that when the 2.5GHz clock is generated, the noise jitter is only 89.0fs RMS, which meets the requirement of the time alternating data acquisition system. Based on the above technology, the project team designs and implements a data acquisition system based on time alternation, which is composed of analog signal input, clock generation and distribution, power management, A / D conversion, etc. Six sub-modules are composed of data receiving buffer and data processing and reporting. The measured results of the whole system performance show that the system achieves the 5GSPS sampling rate and the sampling accuracy reaches more than 8 bits at the same time.
【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TP274.2;TN918.4
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本文編號：1909084