本文選題：衛(wèi)星數(shù)據(jù)傳輸 + 均衡算法　； 參考：《燕山大學(xué)》2014年博士論文

【摘要】：隨著通信網(wǎng)絡(luò)中信息交換量的加大，現(xiàn)代衛(wèi)星高速數(shù)據(jù)傳輸系統(tǒng)的均衡器，需在數(shù)據(jù)吞吐量、幅度誤差和相位誤差抑制能力、算法收斂速度和穩(wěn)態(tài)誤差等方面具有更高的性能指標(biāo)。當(dāng)前Bussgang (巴斯岡)類(lèi)算法，，由于算法性能顯著和計(jì)算復(fù)雜度低，使其在理論研究和實(shí)際工程中呈現(xiàn)巨大價(jià)值。但受限于Bussgang類(lèi)算法本身固有機(jī)制約束，使其對(duì)圓包絡(luò)星座圖特征的調(diào)制信號(hào)在相位誤差抑制上，對(duì)多模值高階調(diào)制信號(hào)在均衡性能上，以及對(duì)算法工程實(shí)現(xiàn)中傳輸數(shù)據(jù)的吞吐量上，均呈現(xiàn)出不足。因此，本文以系統(tǒng)群時(shí)延建模的非線性相頻特性衛(wèi)星信道為基礎(chǔ)，針對(duì)均衡算法的相位誤差抑制能力、多模值調(diào)制信號(hào)的算法性能和均衡器的數(shù)據(jù)吞吐量三個(gè)問(wèn)題展開(kāi)研究。 針對(duì)圓包絡(luò)單模值和多模值星座圖特征的調(diào)制信號(hào)，分別提出星座圖相位匹配算法和象限恒定相位算法，以實(shí)現(xiàn)對(duì)傳輸信號(hào)相位誤差的抑制。根據(jù)圓包絡(luò)單模值調(diào)制信號(hào)的星座圖相位特征，構(gòu)建由正弦函數(shù)組成的星座圖相位誤差匹配項(xiàng)，并通過(guò)與恒模算法代價(jià)函數(shù)進(jìn)行線性加權(quán)，進(jìn)而得到星座圖相位匹配算法。根據(jù)圓包絡(luò)多模值星座圖相位特征，依據(jù)各象限相位統(tǒng)計(jì)量為常數(shù)值的假設(shè)，構(gòu)建相位誤差匹配項(xiàng)，進(jìn)而得到象限恒定相位算法。 針對(duì)多模值圓包絡(luò)和矩形包絡(luò)星座圖特征調(diào)制信號(hào)，分別提出雙模式恒模均衡算法和雙模式多模均衡算法，以使算法在具有穩(wěn)定收斂性能同時(shí)，實(shí)現(xiàn)算法與多模值調(diào)制信號(hào)的星座圖特征相匹配。算法通過(guò)遞歸方程估計(jì)均衡器瞬時(shí)收斂狀態(tài)，根據(jù)均衡器收斂過(guò)程中輸出信號(hào)分布特征的變化規(guī)律，得到收斂狀態(tài)的判決閾值，進(jìn)而實(shí)現(xiàn)對(duì)均衡器的雙模式控制。在算法建立之初，均衡器工作于散度常量模式，以使均衡器獲得穩(wěn)定的收斂性能；在算法建立之后，均衡器工作于散度變量模式，以通過(guò)算法與星座圖匹配，實(shí)現(xiàn)均衡器收斂速度的提高和穩(wěn)態(tài)誤差的降低。 構(gòu)建并行濾波器和流水線算法迭代結(jié)構(gòu)均衡器，以消除電子器件對(duì)均衡器數(shù)據(jù)吞吐量的約束，提高均衡器數(shù)據(jù)吞吐量；提出適應(yīng)該結(jié)構(gòu)均衡算法，以使均衡器在數(shù)據(jù)吞吐量提高的同時(shí)，改善均衡器整體性能。該結(jié)構(gòu)中，并行濾波器用于消除電子器件最大運(yùn)行速率對(duì)數(shù)據(jù)吞吐量的約束，流水線結(jié)構(gòu)用于降低算法迭代過(guò)程對(duì)電子器件實(shí)時(shí)性的削弱，但該結(jié)構(gòu)同時(shí)增大算法迭代周期，降低算法對(duì)傳輸信號(hào)的利用率。因此，根據(jù)梯度下降原理和均衡器抽頭系數(shù)迭代過(guò)程的變化規(guī)律，提出多梯度模式均衡算法。 綜合全文研究?jī)?nèi)容，針對(duì)各種包絡(luò)和模值星座圖特征中代表性調(diào)制方式，正交相移鍵控、8階相移鍵控、16階正交幅度調(diào)制和16階幅相鍵控調(diào)制信號(hào)，給出具有消除電子器件對(duì)數(shù)據(jù)吞吐量約束，實(shí)現(xiàn)相位誤差抑制和多模值特征相匹配能力的均衡器設(shè)計(jì)方案。搭建基于群時(shí)延特征的衛(wèi)星數(shù)據(jù)傳輸測(cè)試平臺(tái)，使用電子器件FPGA實(shí)現(xiàn)各算法設(shè)計(jì)方案，并通過(guò)FPGA輸出信號(hào)的誤差值和星座圖的實(shí)驗(yàn)結(jié)果分析，驗(yàn)證算法有效性。
[Abstract]:With the increase of the information exchange in the communication network , the equalizer of the high - speed data transmission system of the modern satellite has higher performance index in terms of data throughput , amplitude error and phase error suppression capability , algorithm convergence speed and steady - state error .

A constellation diagram phase matching algorithm and a quadrant constant phase algorithm are respectively proposed for the modulation signals of the round envelope single - mode value and the multi - mode value constellation diagram , so as to realize the suppression of the phase error of the transmission signal . According to the constellation phase characteristics of the circular envelope single - mode value modulation signal , a constellation phase matching algorithm is constructed . According to the phase characteristics of the circular envelope multi - mode value constellation map , a phase error matching term is constructed according to the assumption that the phase statistic of each quadrant is a constant value , and then a quadrant constant phase algorithm is obtained .

A dual - mode constant - mode equalization algorithm and a dual - mode multi - mode equalization algorithm are proposed for the multi - mode value circle envelope and the rectangular envelope constellation feature modulation signal . The algorithm is matched with the constellation diagram of the multi - mode value modulated signal . The algorithm estimates the instantaneous convergence state of the equalizer through the recursive equation , and then obtains the decision threshold of the convergence state according to the variation law of the output signal distribution characteristics in the convergence process of the equalizer .
After the algorithm is established , the equalizer operates in the divergence variable mode to match the constellation diagram with the algorithm to realize the improvement of the convergence speed of the equalizer and the reduction of the steady state error .

constructing an iterative structure equalizer of the parallel filter and the pipeline algorithm so as to eliminate the constraint of the electronic device on the equalizer data throughput and improve the data throughput of the equalizer ;
in that structure , the parallel filter is used for eliminating the constraint of the maximum operating speed of the electronic device on the data throughput , and the streamline structure is used for reducing the effect of the algorithm iteration process on the real - time performance of the electronic device , but the structure simultaneously increases the iteration period of the algorithm and reduces the utilization rate of the transmission signal .

In this paper , an equalizer design scheme is given , which can eliminate the constraint of electronic devices on data throughput , realize phase error suppression and multi - mode value characteristic matching .
【學(xué)位授予單位】：燕山大學(xué)
【學(xué)位級(jí)別】：博士
【學(xué)位授予年份】：2014
【分類(lèi)號(hào)】：TN927.2;TN715

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