本文選題：相控陣 + 數(shù)字波束形成��； 參考：《西安電子科技大學》2014年碩士論文

【摘要】：相控陣雷達以其波束靈活性等優(yōu)點突破了常規(guī)雷達的許多限制,使得單部雷達能夠同時完成跟蹤、搜索等多個戰(zhàn)術任務,從而形成了多功能相控陣雷達系統(tǒng)。由于雷達所安放的載體平臺的需要,共形形式的相控陣應運而生,不僅解決了相控陣天線的安放問題,同時提高了雷達與載體平臺的隱身性能。但天線形狀的改變使得相控陣列的波束形成性能不同于常規(guī)規(guī)則幾何布局的相控陣列。本文基于艦載火控相控陣雷達背景,主要針對某種分離折面相控陣進行了數(shù)字波束形成算法的仿真分析。然后通過分析算法需求,進行了基于該陣面的數(shù)字波束形成算法的工程開發(fā)與實現(xiàn)。本文首先從基本的平面相控陣開始,討論了數(shù)字波束形成算法的處理過程及仿真結果。討論了在大尺寸相控陣面下所采用的兩級加權形式的數(shù)字波束形成方法,以及在該形式下的和波束及差波束形成方法。通過逐步對平面陣列進行變換依次形成折面陣和分離形式的折面陣,并對每種形式的陣面進行了和波束及差波束的仿真分析,給出了由于陣面的形狀變化所產(chǎn)生的不同影響。其次本文依據(jù)數(shù)字波束形成算法的計算特點進行了硬件平臺的設計。通過對光纖接收能力、信號處理能力以及數(shù)據(jù)吞吐能力三個方面的分析,提出了硬件平臺的設計要求。依據(jù)設計要求進行了合理的處理芯片選擇,形成了以FPGA和DSP為主的硬件處理平臺。通過對電源、時鐘等主要部分的設計,最終設計出能夠滿足本文所討論的數(shù)字波束形成需要的硬件平臺系統(tǒng)。最后本文在所設計的硬件平臺上進行了數(shù)字波束形成算法的開發(fā)及實現(xiàn)。本文首先以自頂向下的方式對FPGA程序進行了系統(tǒng)設計,給出了一種合理的、可擴展的系統(tǒng)模塊連接方式。然后針對系統(tǒng)中的數(shù)字波束形成計算、FPGA間通信、鏈路口通信等主要模塊進行了詳細設計。其數(shù)字波束形成計算部分基于FPGA內部結構,構建了一種高度并行的計算結構,保證了計算的實時性。針對FPGA間高速通信不穩(wěn)定的問題,在對時序進行了仔細分析后,采用了一種延時補償方式,保證了通信端口的傳輸速率和傳輸性能�；贔PGA設計的特點,本文通過對內部模塊的分析,優(yōu)化了各模塊的內部布局,使得實現(xiàn)結果更加穩(wěn)定。對該平臺內的DSP,本文設計了一種固化啟動方式,克服了傳統(tǒng)代碼包含方法的缺點,并具有更好的普適性和易操作性;同時設計了合理的DSP程序系統(tǒng)流程,簡化了子功能程序設計和后續(xù)擴展。最后以某種波形為測試數(shù)據(jù),對該系統(tǒng)中的每個環(huán)節(jié)及最后結果進行了軟件仿真和在線測試,驗證了設計的可行性和正確性。
[Abstract]:Phased array radar breaks through many limitations of conventional radar because of its advantages such as beam flexibility, which enables single radar to complete multiple tactical tasks such as tracking and searching simultaneously, thus forming a multi-function phased array radar system. Due to the need of carrier platform, conformal phased array emerges as the times require, which not only solves the problem of phased array antenna placement, but also improves the stealth performance of radar and carrier platform. However, the beamforming performance of phased array is different from that of conventional regular geometric layout due to the change of antenna shape. In this paper, based on the background of shipborne fire phased array radar, the digital beamforming algorithm is simulated and analyzed for a separated folded phased array. Then, by analyzing the requirements of the algorithm, the digital beamforming algorithm based on the array surface is developed and implemented. This paper begins with the basic planar phased array and discusses the processing process and simulation results of the digital beamforming algorithm. A two-stage weighted digital beamforming method for large size phased array is discussed, and the sum beam and differential beamforming method in this form are also discussed. By transforming the plane array in turn to form a folded plane array in turn and a folded plane array in separate form, and the simulation analysis of the sum beam and the difference beam of each kind of plane, the different effects caused by the shape change of the array surface are given. Secondly, the hardware platform is designed according to the computing characteristics of digital beamforming algorithm. The design requirements of the hardware platform are put forward through the analysis of the optical fiber receiving ability, the signal processing ability and the data throughput capability. According to the design requirements, the reasonable processing chip selection is carried out, and the hardware processing platform based on FPGA and DSP is formed. Through the design of power supply, clock and other main parts, the hardware platform system which can meet the need of digital beamforming discussed in this paper is designed. Finally, the digital beamforming algorithm is developed and implemented on the hardware platform. In this paper, the FPGA program is designed in a top-down way, and a reasonable and extensible system module connection mode is given. Then the main modules such as communication between FPGA and link intersection are designed in detail. The digital beamforming computing part is based on the internal structure of FPGA, and a highly parallel computing structure is constructed, which ensures the real-time computing. Aiming at the instability of high-speed communication between FPGA, a delay compensation method is adopted after careful analysis of the timing, which ensures the transmission rate and performance of the communication port. Based on the characteristics of FPGA design, this paper optimizes the internal layout of each module by analyzing the internal module, which makes the result more stable. For the DSP in this platform, this paper designs a solidification startup method, which overcomes the shortcomings of the traditional code inclusion method, and has better universality and ease of operation, and also designs a reasonable DSP program system flow. Simplifies subfunction programming and subsequent extensions. Finally, taking a certain waveform as test data, the software simulation and online test of each link and the final results of the system are carried out, and the feasibility and correctness of the design are verified.
【學位授予單位】：西安電子科技大學
【學位級別】：碩士
【學位授予年份】：2014
【分類號】：TN958.92

【引證文獻】

相關會議論文 前1條

1 王冠;夏宇聞;;FPGA設計中的時序分析和約束[A];全國第十屆信號與信息處理、第四屆DSP應用技術聯(lián)合學術會議論文集[C];2006年

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本文編號：1902718