本文選題：全數(shù)字鎖相環(huán) + 線性增強(qiáng)算法　； 參考：《電子科技大學(xué)》2014年碩士論文

【摘要】：鎖相環(huán)作為片內(nèi)高速時(shí)鐘的提供者,在現(xiàn)代電路中至關(guān)重要,幾乎所有的大規(guī)模數(shù)字電路都會(huì)用到鎖相環(huán)。傳統(tǒng)的鎖相環(huán)的性能和面積受到其含有的模擬電路的限制。數(shù)字集成電路抗干擾能力強(qiáng)、可移植性好、面積小和功耗低等優(yōu)點(diǎn)使全數(shù)字的鎖相環(huán)得以廣泛應(yīng)用。時(shí)間數(shù)字轉(zhuǎn)換器(TDC)是全數(shù)字鎖相環(huán)(ADPLL)的重要組成部分,它的分辨率決定了鎖相環(huán)輸出信號(hào)頻率與參考信號(hào)頻率的接近程度,其動(dòng)態(tài)范圍決定了鎖相環(huán)的捕獲范圍和鎖定時(shí)間。本文采用計(jì)數(shù)器和延時(shí)鏈混合結(jié)構(gòu)的TDC,該結(jié)構(gòu)使TDC滿足高分辨率的同時(shí)具有寬的動(dòng)態(tài)范圍。針對(duì)TDC的延時(shí)鏈,本文提出了一種線性增強(qiáng)算法,對(duì)TDC的積分非線性有很大改善。本文首先簡(jiǎn)單介紹了鎖相環(huán)的歷史和研究意義,對(duì)全數(shù)字鎖相環(huán)與傳統(tǒng)鎖相環(huán)的優(yōu)缺點(diǎn)進(jìn)行了比較。然后對(duì)鎖相環(huán)的工作原理、結(jié)構(gòu)和數(shù)學(xué)模型進(jìn)行了介紹,并對(duì)全數(shù)字鎖相環(huán)的工作原理和各個(gè)模塊,包括鑒頻鑒相器(PFD)、時(shí)間數(shù)字轉(zhuǎn)換器(TDC)、數(shù)字環(huán)路濾波器(DLF)和數(shù)控振蕩器(DCO)等的結(jié)構(gòu)和數(shù)學(xué)模型進(jìn)行了詳細(xì)闡述。重點(diǎn)的介紹了線性增強(qiáng)TDC的工作原理和設(shè)計(jì)。最后本文對(duì)所設(shè)計(jì)的全數(shù)字鎖相環(huán)及各個(gè)子模塊的設(shè)計(jì)和仿真進(jìn)行了詳細(xì)描述。本文設(shè)計(jì)的全數(shù)字鎖相環(huán)采用的是0.18μm CMOS工藝,完成了所有電路的設(shè)計(jì)和仿真,且全數(shù)字鎖相環(huán)路的輸出頻率能夠正常鎖定,環(huán)路的鎖定時(shí)間為2μs,其輸出頻率為250MHz,峰峰抖動(dòng)為76ps。
[Abstract]:Phase locked loop (PLL) is very important in modern circuits as the provider of high speed clock in chip. Almost all large scale digital circuits use PLL. The performance and area of traditional PLL are limited by its analog circuit. Digital integrated circuit has the advantages of strong anti-jamming ability, good portability, small area and low power consumption. Time digital converter (TDC) is an important part of all digital phase-locked loop (ADPLL). Its resolution determines the proximity between the output signal frequency and the reference signal frequency, and its dynamic range determines the capture range and locking time of the phase-locked loop. In this paper, TDC with the mixed structure of counter and delay chain is used, which makes the TDC meet the high resolution and has a wide dynamic range. For the delay chain of TDC, a linear enhancement algorithm is proposed, which greatly improves the integral nonlinearity of TDC. In this paper, the history and research significance of PLL are briefly introduced, and the advantages and disadvantages of full digital PLL and traditional PLL are compared. Then the working principle, structure and mathematical model of the PLL are introduced, and the working principle and each module of the all-digital PLL are introduced. The structure and mathematical model of the phase discriminator, time digital converter (TDC), digital loop filter (DLF) and numerical control oscillator (DCO) are described in detail. The working principle and design of linear enhanced TDC are introduced emphatically. Finally, the design and simulation of all digital PLL and its sub-modules are described in detail. The all-digital phase-locked loop designed in this paper uses 0.18 渭 m CMOS technology. All circuits are designed and simulated. The output frequency of the all-digital phase-locked loop can be locked normally. The locking time of the loop is 2 渭 s, the output frequency is 250MHz, and the peak jitter is 76ps.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：TN911.8
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本文編號(hào)：1840092