本文選題：H.264 + FPGA��； 參考：《西安電子科技大學》2014年碩士論文

【摘要】：隨著信息化的不斷發(fā)展,人類社會對于多媒體尤其是視頻信息的需求不斷增多,視頻在會議、網絡點播等諸多應用領域得到快速發(fā)展,在此同時,對視頻質量的要求也在不斷提高。視頻數量的急劇增加以及視頻質量需求的提高,使得視頻存儲以及傳輸的數據量急劇增大,但是網絡帶寬以及存儲空間是有限的,因此實現視頻的高效存儲和傳輸成為實時視頻處理的一個關鍵問題。通過H.264技術的高壓縮率,極大減小了視頻的存儲和傳輸過程中占用的資源,但是,其高壓縮比是通過大量的運算獲得的,會增加系統(tǒng)的運行時間�，F在,FPGA技術的快速發(fā)展為實時視頻處理提供了良好的解決辦法。FPGA等硬件平臺高速并行化的特點,以及廉價和具有豐富邏輯資源的新型FPGA器件的出現,為視頻壓縮的并行化處理提供了良好的條件。論文首先研究了H.264視頻編解碼標準及其編碼原理,重點分析了編碼層實現的主要技術以及影響編碼效率的關鍵因素,對本文所要研究及實現的算法原理及實現方法進行了重點介紹,明確了設計過程中所要解決算法中的關鍵問題。然后闡述了基于FPGA平臺設計的一般方法及Handel-C并行化硬件語言,基于該語言相對于傳統(tǒng)語言具有實現快速、代碼簡潔以及適合軟件工程師使用的特點,提出了使用該語言的H.264幀內編碼設計方法。其次,根據H.264編碼層幀內預測內部結構及工作原理,分析了幀內算法及設計流程,設計了幀內預測算法整體的硬件化結構及功能模塊接口。隨后采用Handel-C設計語言對H.264幀內編碼各個主要功能模塊進行了詳細設計,完成了16×16分塊、4×4分塊、8×8分塊下的幀內各種模式預測和整數變換、量化等模塊的設計實現,并將各模塊整合以實現模式選擇,完成了編碼算法中預測、重構以及模式選擇等過程。建立設計模塊的波形仿真文件,對所設計模塊進行功能仿真。同時,在設計中充分利用Handel-C的語句并行化,提高了算法的執(zhí)行效率。最后對所設計的功能模塊進行了模塊綜合以及仿真驗證。經實驗結果分析,使用Handel-C可以進行FPGA平臺上的H.264算法設計以及實現并可以取得良好的運算性能,驗證了該語言在FPGA平臺上實現視頻壓縮部分算法硬件化的可行性。論文工作對以后其他基于Handel-C高級語言的算法硬化設計以及視頻算法的并行設計具有借鑒意義。
[Abstract]:With the continuous development of information technology, the demand for multimedia, especially video information is increasing in human society. Video has been developed rapidly in many application fields, such as conference, network on demand and so on. At the same time,Video quality requirements are also constantly improving.With the rapid increase of video quantity and the improvement of video quality demand, the amount of video storage and transmission data increases rapidly, but the network bandwidth and storage space are limited.Therefore, the efficient storage and transmission of video becomes a key problem in real-time video processing.The high compression ratio of H.264 greatly reduces the resources consumed in the process of video storage and transmission. However, the high compression ratio is obtained by a large number of operations, which will increase the running time of the system.Now the rapid development of FPGA technology provides a good solution for real-time video processing. FPGA and other hardware platform high-speed parallelization characteristics, as well as cheap and rich logic resources of the emergence of new FPGA devices,It provides a good condition for parallel processing of video compression.Firstly, the H.264 video coding and decoding standard and its coding principle are studied, and the main techniques of the coding layer and the key factors affecting the coding efficiency are analyzed.This paper mainly introduces the principle and method of the algorithm which is to be studied and realized in this paper, and clarifies the key problems to be solved in the process of design.Then the general method of design based on FPGA platform and the parallel hardware language of Handel-C are introduced. Compared with the traditional language, the language has the characteristics of fast realization, simple code and suitable for software engineers.A design method of H. 264 intra coding using this language is presented.Secondly, according to the internal structure and working principle of intra prediction in H.264 coding layer, the intra algorithm and its design flow are analyzed, and the hardware structure and function module interface of the whole intra prediction algorithm are designed.Then, the main function modules of H. 264 intra coding are designed in detail by using Handel-C design language, and the design and implementation of various mode prediction, integer transformation and quantization modules under 16 脳 16 block 4 脳 4 block and 8 脳 8 block are completed.The modules are integrated to realize pattern selection, and the process of prediction, reconstruction and pattern selection in coding algorithm is completed.The waveform simulation file of the design module is established, and the function of the designed module is simulated.At the same time, the parallelization of Handel-C sentences is fully utilized in the design, and the efficiency of the algorithm is improved.Finally, the module synthesis and simulation verification of the designed functional module are carried out.The experimental results show that the H.264 algorithm on FPGA platform can be designed and implemented by using Handel-C, and good performance can be achieved. The feasibility of the hardware implementation of video compression algorithm on FPGA platform is verified.The work of this paper can be used for reference to other algorithms hardening design based on Handel-C and concurrent design of video algorithms.
【學位授予單位】：西安電子科技大學
【學位級別】：碩士
【學位授予年份】：2014
【分類號】：TN919.81

【參考文獻】

相關期刊論文 前1條

1 ;Improved fast inra prediction algorithm of H.264/AVC[J];Journal of Zhejiang University Science A(Science in Engineering);2006年S1期

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本文編號：1749569