本文選題：H.264 + FPGA��； 參考：《西安電子科技大學(xué)》2014年碩士論文

【摘要】：隨著信息化的不斷發(fā)展,人類社會(huì)對(duì)于多媒體尤其是視頻信息的需求不斷增多,視頻在會(huì)議、網(wǎng)絡(luò)點(diǎn)播等諸多應(yīng)用領(lǐng)域得到快速發(fā)展,在此同時(shí),對(duì)視頻質(zhì)量的要求也在不斷提高。視頻數(shù)量的急劇增加以及視頻質(zhì)量需求的提高,使得視頻存儲(chǔ)以及傳輸?shù)臄?shù)據(jù)量急劇增大,但是網(wǎng)絡(luò)帶寬以及存儲(chǔ)空間是有限的,因此實(shí)現(xiàn)視頻的高效存儲(chǔ)和傳輸成為實(shí)時(shí)視頻處理的一個(gè)關(guān)鍵問題。通過H.264技術(shù)的高壓縮率,極大減小了視頻的存儲(chǔ)和傳輸過程中占用的資源,但是,其高壓縮比是通過大量的運(yùn)算獲得的,會(huì)增加系統(tǒng)的運(yùn)行時(shí)間�，F(xiàn)在,FPGA技術(shù)的快速發(fā)展為實(shí)時(shí)視頻處理提供了良好的解決辦法。FPGA等硬件平臺(tái)高速并行化的特點(diǎn),以及廉價(jià)和具有豐富邏輯資源的新型FPGA器件的出現(xiàn),為視頻壓縮的并行化處理提供了良好的條件。論文首先研究了H.264視頻編解碼標(biāo)準(zhǔn)及其編碼原理,重點(diǎn)分析了編碼層實(shí)現(xiàn)的主要技術(shù)以及影響編碼效率的關(guān)鍵因素,對(duì)本文所要研究及實(shí)現(xiàn)的算法原理及實(shí)現(xiàn)方法進(jìn)行了重點(diǎn)介紹,明確了設(shè)計(jì)過程中所要解決算法中的關(guān)鍵問題。然后闡述了基于FPGA平臺(tái)設(shè)計(jì)的一般方法及Handel-C并行化硬件語言,基于該語言相對(duì)于傳統(tǒng)語言具有實(shí)現(xiàn)快速、代碼簡潔以及適合軟件工程師使用的特點(diǎn),提出了使用該語言的H.264幀內(nèi)編碼設(shè)計(jì)方法。其次,根據(jù)H.264編碼層幀內(nèi)預(yù)測(cè)內(nèi)部結(jié)構(gòu)及工作原理,分析了幀內(nèi)算法及設(shè)計(jì)流程,設(shè)計(jì)了幀內(nèi)預(yù)測(cè)算法整體的硬件化結(jié)構(gòu)及功能模塊接口。隨后采用Handel-C設(shè)計(jì)語言對(duì)H.264幀內(nèi)編碼各個(gè)主要功能模塊進(jìn)行了詳細(xì)設(shè)計(jì),完成了16×16分塊、4×4分塊、8×8分塊下的幀內(nèi)各種模式預(yù)測(cè)和整數(shù)變換、量化等模塊的設(shè)計(jì)實(shí)現(xiàn),并將各模塊整合以實(shí)現(xiàn)模式選擇,完成了編碼算法中預(yù)測(cè)、重構(gòu)以及模式選擇等過程。建立設(shè)計(jì)模塊的波形仿真文件,對(duì)所設(shè)計(jì)模塊進(jìn)行功能仿真。同時(shí),在設(shè)計(jì)中充分利用Handel-C的語句并行化,提高了算法的執(zhí)行效率。最后對(duì)所設(shè)計(jì)的功能模塊進(jìn)行了模塊綜合以及仿真驗(yàn)證。經(jīng)實(shí)驗(yàn)結(jié)果分析,使用Handel-C可以進(jìn)行FPGA平臺(tái)上的H.264算法設(shè)計(jì)以及實(shí)現(xiàn)并可以取得良好的運(yùn)算性能,驗(yàn)證了該語言在FPGA平臺(tái)上實(shí)現(xiàn)視頻壓縮部分算法硬件化的可行性。論文工作對(duì)以后其他基于Handel-C高級(jí)語言的算法硬化設(shè)計(jì)以及視頻算法的并行設(shè)計(jì)具有借鑒意義。
[Abstract]:With the continuous development of information technology, the demand for multimedia, especially video information is increasing in human society. Video has been developed rapidly in many application fields, such as conference, network on demand and so on. At the same time,Video quality requirements are also constantly improving.With the rapid increase of video quantity and the improvement of video quality demand, the amount of video storage and transmission data increases rapidly, but the network bandwidth and storage space are limited.Therefore, the efficient storage and transmission of video becomes a key problem in real-time video processing.The high compression ratio of H.264 greatly reduces the resources consumed in the process of video storage and transmission. However, the high compression ratio is obtained by a large number of operations, which will increase the running time of the system.Now the rapid development of FPGA technology provides a good solution for real-time video processing. FPGA and other hardware platform high-speed parallelization characteristics, as well as cheap and rich logic resources of the emergence of new FPGA devices,It provides a good condition for parallel processing of video compression.Firstly, the H.264 video coding and decoding standard and its coding principle are studied, and the main techniques of the coding layer and the key factors affecting the coding efficiency are analyzed.This paper mainly introduces the principle and method of the algorithm which is to be studied and realized in this paper, and clarifies the key problems to be solved in the process of design.Then the general method of design based on FPGA platform and the parallel hardware language of Handel-C are introduced. Compared with the traditional language, the language has the characteristics of fast realization, simple code and suitable for software engineers.A design method of H. 264 intra coding using this language is presented.Secondly, according to the internal structure and working principle of intra prediction in H.264 coding layer, the intra algorithm and its design flow are analyzed, and the hardware structure and function module interface of the whole intra prediction algorithm are designed.Then, the main function modules of H. 264 intra coding are designed in detail by using Handel-C design language, and the design and implementation of various mode prediction, integer transformation and quantization modules under 16 脳 16 block 4 脳 4 block and 8 脳 8 block are completed.The modules are integrated to realize pattern selection, and the process of prediction, reconstruction and pattern selection in coding algorithm is completed.The waveform simulation file of the design module is established, and the function of the designed module is simulated.At the same time, the parallelization of Handel-C sentences is fully utilized in the design, and the efficiency of the algorithm is improved.Finally, the module synthesis and simulation verification of the designed functional module are carried out.The experimental results show that the H.264 algorithm on FPGA platform can be designed and implemented by using Handel-C, and good performance can be achieved. The feasibility of the hardware implementation of video compression algorithm on FPGA platform is verified.The work of this paper can be used for reference to other algorithms hardening design based on Handel-C and concurrent design of video algorithms.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：TN919.81

【參考文獻(xiàn)】

相關(guān)期刊論文 前1條

1 ;Improved fast inra prediction algorithm of H.264/AVC[J];Journal of Zhejiang University Science A(Science in Engineering);2006年S1期

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本文編號(hào)：1749569