本文選題：離散三角變換 + 坐標(biāo)旋轉(zhuǎn)數(shù)字計算機��； 參考：《哈爾濱工業(yè)大學(xué)》2014年博士論文

【摘要】：離散三角變換（Discrete Trigonometic Transform, DTT）在信息處理，尤其是視頻、圖像處理領(lǐng)域具有非常重要的地位和應(yīng)用，其快速算法及硬件實現(xiàn)一直是信息處理領(lǐng)域的研究熱點。新視頻壓縮標(biāo)準(zhǔn)H.265/HEVC發(fā)布后，傳統(tǒng)的典型點數(shù)DTT已不能滿足實際應(yīng)用要求，大點數(shù)（尤其是2n點）、可變點數(shù)的快速算法將成為該領(lǐng)域的研究熱點。 在視頻、圖像處理領(lǐng)域，精確計算DTT的硬件實現(xiàn)方式已基本成熟，采用近似計算成為提高其計算速度的另一有效途徑。隨著使用者對圖像品質(zhì)、處理速度要求不斷提高，采用一種編碼方式已不能滿足應(yīng)用要求。視頻、圖像壓縮編碼正向多正交變換混合編碼方向發(fā)展，設(shè)計出能實現(xiàn)多種正交變換且性能優(yōu)良的通用架構(gòu)（Unified architecture）是亟待解決的問題。 本文針對以上研究熱點問題，對大點數(shù)（2n點）DTT的快速算法及其基于改進(jìn)型非重疊CORDIC的硬件實現(xiàn)以及離散正交變換的通用架構(gòu)展開研究，主要研究工作包括： 1、研究了以CORDIC作為變換核函數(shù)的任意2n點DTT快速算法。首先，通過奇偶分解推導(dǎo)出了以CORDIC作為變換核函數(shù)的任意2n點DCT-II和DST-II的快速算法，并給出了規(guī)律一致的信號流圖；然后，根據(jù)正交變換的對偶原理得到了DCT-III和DST-III的快速算法及其信號流圖，從而提出了一種新型的基于CORDIC的基-2DTT快速算法。與現(xiàn)有算法比較，該算法在硬件復(fù)雜度、可擴展性、流水線設(shè)計、模塊化設(shè)計等性能指標(biāo)上優(yōu)于同類算法，且具有以下突出特點：適用于任意2n點的DTT；既有較低的算法復(fù)雜度又易于VLSI硬件實現(xiàn)；算法中CORDIC的旋轉(zhuǎn)角度為等差數(shù)列；具有規(guī)則的蝶形運算結(jié)構(gòu)和統(tǒng)一的縮放因子，易于實現(xiàn)流水線設(shè)計；支持原位運算等。 2、研究了基于非重疊CORDIC處理單元的DTT硬件實現(xiàn)方法。首先，針對傳統(tǒng)非重疊CORDIC算法中迭代次數(shù)與計算精度相互制約的問題，提出了一種改進(jìn)型非重疊CORDIC（MCORDIC），以犧牲極少精度為代價將迭代次數(shù)減少了50%；然后，根據(jù)所提出的算法中CORDIC的旋轉(zhuǎn)角度為等差數(shù)列這一特點，采用復(fù)用設(shè)計和模塊化設(shè)計思想，大幅度減少了計算DTT所需的CORDIC運算單元的數(shù)量和類型，理論上任意2n點的DTT僅需要一種類型CORDIC；在此基礎(chǔ)上提出了一種新型DTT脈動陣列設(shè)計方法，基于該方法設(shè)計的脈動陣列在電路延遲、吞吐率、流水線操作及硬件復(fù)雜度等性能指標(biāo)上優(yōu)于其他類似架構(gòu)，并解決了由于存在不同類型的基本運算單元（PE）而導(dǎo)致的計算時序不同步以及PE中存在多種算術(shù)運算等問題。 3、以所提出的快速算法為研究基礎(chǔ)，對四種類型DTT之間的內(nèi)在關(guān)系進(jìn)行了探討。利用相同點數(shù)的DTT具有相同的CORDIC運算單元這一特點，通過控制信號流向來實現(xiàn)不同類型DTT的計算，從而提出了一種基于CORDIC的DTT通用架構(gòu)設(shè)計方法。所提出的方法適用于任意2n點DTT，，可實現(xiàn)四種DTT的任意組合的通用架構(gòu)，并且具有以下優(yōu)點：具有統(tǒng)一的變換核函數(shù)，控制電路簡單，硬件復(fù)用率高。利用該方法設(shè)計了具有代表性的幾種通用架構(gòu)，所設(shè)計的架構(gòu)在硬件復(fù)雜度、控制復(fù)雜度、吞吐率、可擴展性、模塊化程度、流水線設(shè)計等性能指標(biāo)上優(yōu)于現(xiàn)有通用架構(gòu)。此外，還給出了DWHT/DCT-II和Haar-DWT/DCT-II通用架構(gòu)的設(shè)計方法。 4、在Haar-DWT/DCT-II通用架構(gòu)的基礎(chǔ)上，研究了基于圖像內(nèi)容的壓縮編碼硬件實現(xiàn)架構(gòu)。該架構(gòu)以圖像的JND值為判斷依據(jù)有選擇的進(jìn)行圖像壓縮編碼。為解決JND計算復(fù)雜度高、難于硬件實現(xiàn)的問題，提出了一種基于Haar-DWT的近似計算JND算法，該算法雖然只得到JND的近似解，卻大幅度降低了計算復(fù)雜度。設(shè)計了可實現(xiàn)兩種工作模式（近似計算或非近似計算）的可重構(gòu)DCT-II架構(gòu)。研究了基于圖像內(nèi)容壓縮編碼的控制方案、工作模式選取的參考位置和JND閾值的選取方法。實驗結(jié)果表明該壓縮編碼架構(gòu)切實可行。所設(shè)計的壓縮編碼硬件實現(xiàn)架構(gòu)中沒有復(fù)雜的算術(shù)運算，計算復(fù)雜度非常低，因此非常易于VLSI硬件實現(xiàn)。 本文提出了一種新型的以CORDIC作為變換核函數(shù)的DTT快速算法，為研究DTT快速算法提供了新的研究思路和方法。研究的近似計算DTT的VLSI實現(xiàn)方式及其通用架構(gòu)可以滿足視頻、圖像壓縮領(lǐng)域目前的需求，并符合未來該領(lǐng)域的發(fā)展方向。正如FFT的提出使得DFT在實際應(yīng)用中得到飛躍性的發(fā)展，具有類似FFT特點的DTT快速算法也將使得DTT得到更廣泛的應(yīng)用。論文所研究內(nèi)容既具有理論研究的前瞻性又具有現(xiàn)實的應(yīng)用價值。
[Abstract]:Discrete triangular transform ( DTT ) plays a very important role in information processing , especially in video and image processing . Its fast algorithm and hardware implementation have been hot topics in the field of information processing .

In the field of video and image processing , it is an effective way to accurately calculate the hardware realization mode of DTT , and the approximate calculation is adopted as another effective way to improve its computing speed . With the improvement of image quality and processing speed , the application requirement can not be satisfied by adopting a coding mode .

In this paper , based on the above research hot - point problems , the fast algorithm of large - point ( 2n - point ) DTT and its hardware realization based on improved non - overlapping CORDIC and the general framework of discrete orthogonal transformation are studied .

1 . The fast algorithm of arbitrary 2n - point DTT using CORDIC as the transform kernel function is studied . First , the fast algorithm of arbitrary 2n - point DCT - II and DST - II using CORDIC as the transform kernel function is derived by the parity decomposition , and the regular signal flow diagram is given .
Then , the fast algorithm and signal flow diagram of DCT - III and DST - III are obtained according to the duality principle of orthogonal transformation , and a new fast algorithm based on CORDIC based radix - 2DTT is proposed . Compared with the existing algorithm , the algorithm is superior to similar algorithms in terms of hardware complexity , scalability , pipeline design , modular design and the like , and has the following prominent characteristics :
has low algorithm complexity and easy VLSI hardware implementation ;
the rotation angle of the CORDIC in the algorithm is an equal number column ;
the invention has regular butterfly operation structure and uniform scaling factor , and is easy to realize pipeline design ;
support in - situ computing or the like .

2 . The realization method of DTT hardware based on non - overlapping CORDIC processing unit is studied . First , aiming at the problem of mutual restriction between the number of iterations and the calculation precision in the traditional non - overlapping CORDIC algorithm , an improved non - overlapping CORDIC ( MCORDIC ) is proposed to reduce the number of iterations by 50 % at the cost of very little precision .
Then , according to the characteristics of CORDIC in the proposed algorithm , the number and the types of CORDIC arithmetic units required for calculating DTT are greatly reduced by using multiplexing design and modular design idea , and only one kind of CORDIC is needed for any 2n point in theory .
On the basis of this , a novel design method of DTT pulse array is presented , which is superior to other similar architectures in terms of circuit delay , throughput rate , pipeline operation and hardware complexity based on the design of the method , and solves the problems of non - synchronization of computing timing due to the existence of different types of basic arithmetic units ( PE ) and the existence of various arithmetic operations in PE .

3 . Based on the proposed fast algorithm , the intrinsic relationship between the four kinds of DTT is discussed . A universal architecture based on CORDIC is proposed . The proposed method is suitable for any 2n - point DTT . It has the advantages of simple control circuit and high hardware reuse . The proposed architecture is superior to the existing general architecture in terms of hardware complexity , control complexity , throughput , scalability , modularity , pipeline design , etc . The design method of DWHT / DCT - II and Haar - DWT / DCT - II general architecture is also given .

4 . Based on the general architecture of Haar - DWT / DCT - II , the hardware implementation architecture of compression coding based on image content is studied .

This paper presents a novel DTT fast algorithm with CORDIC as a transform kernel function , which provides a new research thinking and method for the study of DTT fast algorithm . The VLSI implementation of DTT and its general architecture can meet the current demands in the field of video and image compression .

【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級別】：博士
【學(xué)位授予年份】：2014
【分類號】：TN919.81

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相關(guān)期刊論文 前2條

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