本文選題：雷達回波模擬器 + 存儲器��； 參考：《西安電子科技大學》2015年碩士論文

【摘要】：隨著軍隊電子化水平的快速提升,雷達的作用日益凸顯,雷達系統(tǒng)的研制越發(fā)地重要和急切。在雷達系統(tǒng)中,信號處理機的作用十分重要,需要經(jīng)過多次試驗來檢驗信號處理機對回波數(shù)據(jù)的處理能力。然而,試驗通常是在外場進行,一方面,外場試驗成本高,容易受環(huán)境等外部因素的影響;另一方面,鑒于雷達系統(tǒng)調試是整機調試,如果出現(xiàn)問題,需要對整個雷達系統(tǒng)進行檢查進而對問題定位,調試過程比較麻煩。為了解決上述問題,國內外逐漸開始使用雷達回波模擬器對信號處理機進行監(jiān)控測試。這樣不僅節(jié)省了人力資源和成本花費,而且方便了調試,很大程度上縮短了雷達系統(tǒng)的研制開發(fā)時間。本文講述的數(shù)字陣列雷達回波模擬器采用的是PC機+FPGA的結構,包括數(shù)據(jù)的產生和數(shù)據(jù)的存儲轉換兩部分。數(shù)據(jù)的產生是基于PC機中對應的信號模擬軟件實現(xiàn),包括各種模擬目標信號和各種雜波信號,并將其存儲在PC機硬盤中,通過PCI協(xié)議傳輸?shù)侥M器存儲設備中;數(shù)據(jù)的存儲轉換主要是以FPGA為控制核心,各種接口和存儲芯片(NAND FLASH)為輔助設計。一方面,本文講述的模擬器不但可以使用光纖接收發(fā)送數(shù)據(jù),同時可以使用網(wǎng)口完成模擬器與局域網(wǎng)中的PC機通信;另一方面,本設計既可以實現(xiàn)將一路陣列信號轉化為四十路的陣列信號,也可以為接收的四十路信號加線性調頻信號。設計主要有三塊電路板,一塊是接口板,主要用于控制存儲的數(shù)據(jù)與外界之間的傳輸;另外兩塊是存儲板,含有大量存儲芯片,主要用于存儲各種數(shù)據(jù)。本文的主要內容有:(1)完成模擬器硬件電路的設計,并對設計中相關芯片進行了功能介紹;(2)將PC機產生的一路模擬信號經(jīng)過CPCI背板由計算機硬盤導入到模擬器的存儲設備中,并且經(jīng)過處理轉化為40路模擬信號,然后將信號數(shù)據(jù)存儲起來等待回放;(3)使用光纖接收40路實時信號,并將信號存儲到存儲設備中,在輸出該信號時,每路信號上添加一路線性調頻信號作為輔助檢測信號;(4)實現(xiàn)PC機和存儲設備之間的網(wǎng)口通信。雷達回波模擬器中,各種通信接口起著至關重要的作用,它們是模擬器與外界進行數(shù)據(jù)傳輸?shù)募~帶,只有通過它們才能實現(xiàn)數(shù)據(jù)的傳輸,其中,接口時序的設計是模擬器設計的關鍵,決定著數(shù)據(jù)能否正確穩(wěn)定的傳輸。
[Abstract]:With the rapid improvement of military electronic level, the role of radar is increasingly prominent, the development of radar system is more and more important and urgent.In radar system, the function of signal processor is very important. It is necessary to test the ability of signal processor to deal with echo data through many experiments.However, the test is usually conducted in the field. On the one hand, the cost of the field test is high, and it is easily affected by external factors such as environment. On the other hand, since the debugging of the radar system is the debugging of the whole machine, if there is a problem,Need to check the entire radar system and then locate the problem, debugging process is more troublesome.In order to solve the above problems, radar echo simulator has been used to monitor and test the signal processor at home and abroad.This not only saves human resource and cost, but also facilitates debugging and shortens the time of radar system research and development to a great extent.The digital array radar echo simulator described in this paper uses the structure of PC FPGA, including data generation and data storage conversion.The data generation is based on the corresponding signal simulation software in PC, including various analog target signals and clutter signals, which are stored in the PC hard disk and transmitted to the simulator storage device through PCI protocol.Data storage conversion is mainly based on FPGA as the control core and various interfaces and memory chips as the aid design.On the one hand, the simulator described in this paper can not only use optical fiber to receive and send data, but also use network interface to complete the communication between simulator and PC in LAN; on the other hand,This design can not only transform one array signal into 40 channel array signal, but also add linear frequency modulation signal to the received 40 channel signal.There are mainly three circuit boards, one is an interface board, mainly used to control the transmission between stored data and the outside world; the other two are memory boards, containing a large number of memory chips, mainly used to store all kinds of data.The main contents of this paper are as follows: 1) complete the hardware circuit design of simulator, and introduce the function of related chip in the design. (2) the analog signal generated by PC is imported from the computer hard disk to the memory device of simulator through the CPCI backplane.After processing, the signal is converted into a 40-channel analog signal, and then the signal data is stored to wait for playback. (3) using optical fiber to receive 40 real-time signals, and storing the signal in the storage device, when the signal is output,A linear frequency modulation (LFM) signal is added to each signal as an auxiliary detection signal to realize the communication between PC and storage device.In radar echo simulator, various communication interfaces play an important role. They are the link between the simulator and the outside world. Only through them can the data be transmitted.The design of interface timing is the key of simulator design, which determines whether the data can be transmitted correctly and stably.
【學位授予單位】：西安電子科技大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN955

【參考文獻】

相關期刊論文 前10條

1 張凱;朱新國;;數(shù)字陣列雷達多目標模擬器設計[J];現(xiàn)代雷達;2014年01期

2 劉棟;馬強;;一種雷達目標模擬器的設計[J];電子技術;2013年06期

3 胡萬坤;潘瑞云;沈磊;;數(shù)字陣列雷達目標模擬器設計[J];雷達與對抗;2013年01期

4 高建棟;韓壯志;何強;郭寶鋒;;雷達回波模擬器的研究與發(fā)展[J];飛航導彈;2013年01期

5 邾琳琳;譚劍波;張卿;;基于控制接口芯片的波控系統(tǒng)設計[J];國外電子測量技術;2011年05期

6 陳曾平;張月;鮑慶龍;;數(shù)字陣列雷達及其關鍵技術進展[J];國防科技大學學報;2010年06期

7 詹俊鵬;李鵬;;基于Altera FPGA的千兆以太網(wǎng)實現(xiàn)方案[J];電子設計工程;2009年02期

8 龍偉軍;王f，

本文編號：1741268