本文選題：低密度奇偶校驗(yàn)碼　切入點(diǎn)：準(zhǔn)雙對(duì)角線　出處：《國(guó)防科學(xué)技術(shù)大學(xué)》2015年碩士論文

【摘要】：低密度奇偶校驗(yàn)碼采用稀疏奇偶校驗(yàn)矩陣進(jìn)行構(gòu)造,是一類特殊的線性分組碼,它具有逼近Shannon限的優(yōu)異糾錯(cuò)編碼性能。該碼適用于具有傳輸距離遠(yuǎn)、信號(hào)衰減大、信號(hào)發(fā)送功率受限等特點(diǎn)的空間通信信道。然而,LDPC碼編碼過(guò)程通常具有較高的復(fù)雜性,在一定程度上制約了它在實(shí)際中的普遍應(yīng)用。對(duì)此,本文在空間通信應(yīng)用背景下,對(duì)如何設(shè)計(jì)性能優(yōu)、復(fù)雜度低的譯碼器進(jìn)行了研究,主要工作如下:首先,在對(duì)LDPC碼的構(gòu)造方法和編碼算法研究的基礎(chǔ)上,提出了一種采用準(zhǔn)雙對(duì)角線結(jié)構(gòu)構(gòu)造奇偶校驗(yàn)矩陣的方法。此種方法繼承了IEEE802.16e標(biāo)準(zhǔn)LDPC碼的準(zhǔn)雙對(duì)角線結(jié)構(gòu),并且在構(gòu)造時(shí)消除了對(duì)基礎(chǔ)矩陣擴(kuò)展因子的約束條件。通過(guò)改進(jìn),不但構(gòu)造出的LDPC碼編碼簡(jiǎn)單,而且可以根據(jù)設(shè)計(jì)的不同需求,靈活構(gòu)造出多種不同碼長(zhǎng)和碼率組合的LDPC碼,適用范圍更廣,更加貼近空間通信的工程應(yīng)用需求。本文選用(16384,8192)LDPC碼,采用這種方法對(duì)H矩陣進(jìn)行構(gòu)造,給出了快速編碼算法和編碼電路設(shè)計(jì)。然后,針對(duì)空間數(shù)據(jù)咨詢委員會(huì)(CCSDS)推薦的幾種深空和近地應(yīng)用的LDPC碼,采用傳統(tǒng)譯碼算法,分別設(shè)定不同譯碼算法、迭代次數(shù)、碼長(zhǎng)和碼率分析其對(duì)誤碼率的影響,尋找出有利于LDPC碼譯碼器硬件實(shí)現(xiàn)的歸一化最小和譯碼算法。通過(guò)對(duì)傳統(tǒng)并行算法消息傳遞方式的改進(jìn),將串行消息傳遞機(jī)制應(yīng)用于歸一化最小和譯碼算法中。串行算法相對(duì)于傳統(tǒng)并行算法,減少了消息更新的迭代次數(shù)和運(yùn)算量,能夠改善譯碼的收斂性、降低數(shù)據(jù)存儲(chǔ)量,更適合低復(fù)雜度的譯碼器設(shè)計(jì)。對(duì)本設(shè)計(jì)中構(gòu)造的(16384,8192)LDPC碼采用串行歸一化最小和算法進(jìn)行譯碼仿真,能夠取得優(yōu)異的誤碼率性能。最后,完成(16384,8192)LDPC碼譯碼器的FPGA硬件實(shí)現(xiàn)。通過(guò)對(duì)最大迭代次數(shù)、歸一化因子、數(shù)據(jù)量化方式等影響譯碼性能的重要因素進(jìn)行仿真分析,基于FPGA對(duì)譯碼器頂層電路和功能模塊進(jìn)行設(shè)計(jì)和優(yōu)化,完成了(16384,8192)LDPC碼譯碼器的硬件實(shí)現(xiàn)。通過(guò)測(cè)試驗(yàn)證,本文的設(shè)計(jì)方法可以實(shí)現(xiàn)高譯碼性能、低實(shí)現(xiàn)復(fù)雜度的LDPC碼譯碼器,能夠較好的應(yīng)用于空間通信的相關(guān)領(lǐng)域。
[Abstract]:Low-density parity-check codes are constructed by sparse parity check matrices. They are a special class of linear block codes with excellent error-correcting performance which approximates the Shannon limit.The code is suitable for space communication channels with long transmission distance, large signal attenuation and limited signal transmission power.However, the coding process of LDPC codes usually has high complexity, which restricts its general application in practice to some extent.In this paper, under the background of space communication application, we study how to design a decoder with good performance and low complexity. The main work is as follows: firstly, based on the research of the construction method and coding algorithm of LDPC code,A method of constructing parity check matrix with quasi-bidiagonal structure is presented.This method inherits the quasi-bidiagonal structure of the IEEE802.16e standard LDPC code and eliminates the constraint on the expansion factor of the basic matrix.Through the improvement, not only the LDPC codes constructed are simple, but also the LDPC codes with different code length and rate combination can be flexibly constructed according to the different requirements of the design, and the application range is wider and closer to the engineering application requirements of space communication.In this paper, the H matrix is constructed by using this method, and the fast coding algorithm and the design of coding circuit are given.Then, for several kinds of deep space and near-ground LDPC codes recommended by the Space data Advisory Committee, the traditional decoding algorithms are used to set different decoding algorithms, the number of iterations, the code length and the bit rate to analyze their influence on the bit error rate (BER).A normalized minimum and decoding algorithm is found for the hardware implementation of LDPC decoder.Through the improvement of the traditional parallel algorithm, the serial message passing mechanism is applied to the normalized minimum and decoding algorithm.Compared with the traditional parallel algorithm, the serial algorithm reduces the number of iterations and operations of message update, improves the convergence of decoding, reduces the data storage, and is more suitable for the design of low complexity decoder.In this paper, the serial normalized minimum sum algorithm is used to decode and simulate the LDPC code constructed in this design, which can achieve excellent bit error rate (BER) performance.Finally, the FPGA hardware implementation of the LDPC decoder is completed.Through the simulation and analysis of the most important factors such as the number of iterations, normalization factor, data quantization and other important factors affecting the decoding performance, the design and optimization of the top-level circuit and function module of the decoder based on FPGA are carried out.The hardware implementation of the LDPC decoder is completed.The test results show that the design method of this paper can achieve high decoding performance and low implementation complexity of LDPC decoder, and can be used in space communication field.
【學(xué)位授予單位】：國(guó)防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN911.22

【參考文獻(xiàn)】

相關(guān)期刊論文 前4條

1 張仲明;許拔;楊軍;張爾揚(yáng);;800Mbps準(zhǔn)循環(huán)LDPC碼譯碼器的FPGA實(shí)現(xiàn)[J];信號(hào)處理;2010年02期

2 管武;董明科;項(xiàng)海格;;應(yīng)用循環(huán)移位矩陣設(shè)計(jì)LDPC碼譯碼器[J];應(yīng)用科學(xué)學(xué)報(bào);2009年02期

3 丁溯泉;;ARA LDPC碼在深空測(cè)控通信系統(tǒng)中的應(yīng)用[J];飛行器測(cè)控學(xué)報(bào);2009年01期

4 雷菁;王建輝;唐朝京;;基于PEG算法的準(zhǔn)循環(huán)擴(kuò)展LDPC碼構(gòu)造[J];通信學(xué)報(bào);2008年09期

相關(guān)博士學(xué)位論文 前2條

1 張仲明;高速數(shù)傳中LDPC碼關(guān)鍵技術(shù)研究[D];國(guó)防科學(xué)技術(shù)大學(xué);2009年

2 雷菁;低復(fù)雜度LDPC碼構(gòu)造及譯碼研究[D];國(guó)防科學(xué)技術(shù)大學(xué);2009年

，

本文編號(hào)：1689855