本文選題：現(xiàn)場(chǎng)可編程門陣列　切入點(diǎn)：雷達(dá)信號(hào)處理　出處：《西安電子科技大學(xué)》2014年碩士論文

【摘要】：近年來(lái),隨著雷達(dá)及其相關(guān)領(lǐng)域技術(shù)的發(fā)展,雷達(dá)在人類生活及軍事中肩負(fù)起越來(lái)越重要的責(zé)任。雷達(dá)信號(hào)處理系統(tǒng)作為雷達(dá)系統(tǒng)的重要組成部分,近年來(lái)也隨著DSP和FPGA的大量引入發(fā)展迅速。特別是FPGA具備可并行處理、體積小、速度快等特點(diǎn),在各數(shù)字系統(tǒng)中使用量大大增加。FPGA已經(jīng)具備實(shí)現(xiàn)整個(gè)雷達(dá)信號(hào)處理的能力,因此基于FPGA數(shù)字信號(hào)處理的實(shí)現(xiàn)在雷達(dá)信號(hào)處理中占有重要地位。本文針對(duì)FPGA在雷達(dá)系統(tǒng)設(shè)計(jì)中的應(yīng)用技術(shù)展開(kāi)研究,主要講述三部分內(nèi)容:1.詳細(xì)介紹了雷達(dá)信號(hào)處理算法和多功能性設(shè)計(jì)�，F(xiàn)代雷達(dá)對(duì)其功能的要求越來(lái)越多樣化。針對(duì)這一要求,本文設(shè)計(jì)的信號(hào)處理系統(tǒng)可根據(jù)不同需求適時(shí)改變工作模式。針對(duì)不同的工作模式,各個(gè)信號(hào)處理算法參數(shù)可實(shí)現(xiàn)實(shí)時(shí)配置。隨后依次介紹了雷達(dá)信號(hào)處理的基本算法理論。重點(diǎn)研究了FIR實(shí)現(xiàn)自適應(yīng)MTD濾波器的設(shè)計(jì)方法,并進(jìn)一步介紹了滑動(dòng)MTD實(shí)現(xiàn)方法。2.詳細(xì)介紹了雷達(dá)信號(hào)處理檢測(cè)算法。雷達(dá)的根本任務(wù)是檢測(cè)目標(biāo),雷達(dá)信號(hào)處理的目的也是提高檢測(cè)概率。首先介紹了CFAR檢測(cè)的基本原理。然后按其處理方式分類分別研究了單元平均恒虛警檢測(cè)和雜波圖恒虛警檢測(cè)。針對(duì)單元平均恒虛警檢測(cè)分別研究了單元平均、單元平均選大、單元平均選小3種恒虛警處理方法,并進(jìn)一步給出了其二維實(shí)現(xiàn)的方法。針對(duì)各恒虛警檢測(cè)方法,本文從檢測(cè)概率及檢測(cè)損失兩個(gè)方面分析了其各自的檢測(cè)性能。3.結(jié)合實(shí)際工程項(xiàng)目,詳細(xì)介紹了某雷達(dá)系統(tǒng)的FPGA設(shè)計(jì)。該雷達(dá)信號(hào)處理系統(tǒng)由AD定時(shí)采樣板及多塊信號(hào)處理板組成。信號(hào)處理由FPGA和DSP共同實(shí)現(xiàn)。FPGA完成定時(shí)控制、AD采樣、數(shù)字下變頻、脈沖壓縮、恒虛警檢測(cè)及與各雷達(dá)系統(tǒng)通信等工作。依次介紹了FPGA各模塊的程序設(shè)計(jì)及實(shí)現(xiàn)方法,重點(diǎn)描述了脈沖壓縮模塊和定時(shí)控制模塊。脈沖壓縮模塊采用分時(shí)復(fù)用FFT核的方法實(shí)現(xiàn)了多通道大數(shù)據(jù)量的脈沖壓縮處理。定時(shí)控制模塊實(shí)現(xiàn)了多工作模式雷達(dá)的復(fù)雜時(shí)序控制。經(jīng)過(guò)實(shí)驗(yàn)室調(diào)試和外場(chǎng)實(shí)測(cè)驗(yàn)證后,FPGA工作正常,信號(hào)處理系統(tǒng)實(shí)現(xiàn)了預(yù)期功能。
[Abstract]:In recent years, with the development of radar and its related technology, radar is shouldering more and more important responsibility in human life and military affairs. Radar signal processing system is an important part of radar system. In recent years, with the rapid development of DSP and FPGA, especially FPGA has the characteristics of parallel processing, small size, fast speed, and so on. The use of FPGA has been greatly increased in various digital systems. FPGA has the ability to realize the whole radar signal processing. Therefore, the realization of digital signal processing based on FPGA plays an important role in radar signal processing. In this paper, the application technology of FPGA in radar system design is studied. This paper introduces the radar signal processing algorithm and multifunctional design in detail. The requirements of modern radar for its functions are becoming more and more diversified. The signal processing system designed in this paper can change the working mode according to different demands. The parameters of each signal processing algorithm can be configured in real time. Then the basic algorithm theory of radar signal processing is introduced in turn. The design method of adaptive MTD filter based on FIR is studied emphatically. The realization method of sliding MTD. 2. The detection algorithm of radar signal processing is introduced in detail. The basic task of radar is to detect the target. The purpose of radar signal processing is also to improve the detection probability. Firstly, the basic principle of CFAR detection is introduced. Then, the unit average CFAR detection and clutter map CFAR detection are studied according to their processing methods. The average CFAR detection has studied the unit average, There are three CFAR processing methods, one is the average size of the unit and the other is the average selection of the unit, and the two dimensional realization method is also given, which is aimed at each CFAR detection method. This paper analyzes their detection performance from two aspects: detection probability and detection loss. The FPGA design of a radar system is introduced in detail. The radar signal processing system is composed of AD timing sampling board and multiple signal processing boards. The signal processing is implemented by FPGA and DSP to complete timing control AD sampling, digital downconversion, pulse compression, etc. CFAR detection and communication with radar systems are introduced. The program design and implementation method of each module of FPGA are introduced in turn. The pulse compression module and the timing control module are described in detail. The pulse compression module uses the time-sharing multiplexing FFT core to realize the pulse compression processing of the multi-channel large data volume. The timing control module realizes the multi-mode radar. After laboratory debugging and field testing, FPGA works normally. The signal processing system realizes the expected function.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：TN957.51;TN791

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