本文選題：深空通信　切入點：LDPC碼　出處：《哈爾濱工業(yè)大學》2014年碩士論文

【摘要】：LDPC碼在深空通信中有很好的實用價值，同時LDPC碼也被廣泛應用于光纖通信、衛(wèi)星數(shù)字視頻和音頻廣播等領域。在加性高斯白噪聲信道環(huán)境下，BPSK調(diào)制時，歸一化最小和譯碼算法能很好地平衡譯碼性能和算法復雜度，易于硬件實現(xiàn)，且常以流水線的形式出現(xiàn)在譯碼器的設計中。本文針對LDPC譯碼器提出一種新的設計思路，將流水線思想從譯碼算法本身擴展到譯碼器的整體設計中，設計出可以多幀并行且結(jié)構(gòu)簡單的譯碼器，最后通過仿真與實現(xiàn)對其性能進行驗證。本文主要的研究工作如下： 首先，利用雙對角QC-LDPC碼校驗矩陣的特點，設計雙遞歸流水線編碼器，詳細介紹其編碼原理與編碼器的結(jié)構(gòu)，并細致分析編碼器的工作流程，給出仿真時序圖與資源消耗情況。 其次，按照LDPC碼譯碼算法的演化進程對概率域BP算法、對數(shù)域BP算法以及歸一化最小和算法分別進行介紹，并對它們的性能進行仿真比較。然后分別對歸一化系數(shù)、迭代次數(shù)以及初始值量化位數(shù)等譯碼參數(shù)進行性能仿真，并根據(jù)仿真結(jié)果做出適當?shù)倪x擇。 之后，提出流水線式譯碼器的設計思想，給出歸一化最小和譯碼算法的流水線化方法，詳細介紹流水線式譯碼器的結(jié)構(gòu)與工作原理，針對規(guī)則與準循環(huán)LDPC碼設計兩款譯碼器，并給出仿真結(jié)果，提出進一步優(yōu)化的方向。 最后，將兩組編碼器和譯碼器在FPGA實驗板上進行實現(xiàn)，在Matlab以及串口調(diào)試助手等軟件的幫助下，通過串口與計算機進行配合，組成兩套編譯碼系統(tǒng)，，實現(xiàn)數(shù)據(jù)的編譯碼工作，并檢驗編譯碼器在實際應用中的性能。
[Abstract]:LDPC codes have good practical value in deep space communication, and LDPC codes are also widely used in optical fiber communication, satellite digital video and audio broadcasting. The normalized minimum sum decoding algorithm can balance decoding performance and algorithm complexity well, and is easy to implement in hardware, and often appears in the design of decoder in the form of pipeline. This paper presents a new design idea for LDPC decoder. This paper extends pipeline's idea from decoding algorithm to the whole design of decoder, designs a decoder that can be parallel in multiple frames and has simple structure, and finally verifies its performance by simulation and implementation. The main research work of this paper is as follows:. Firstly, based on the characteristics of double-diagonal QC-LDPC code check matrix, a double-recursion pipeline encoder is designed, its coding principle and encoder structure are introduced in detail, the working flow of encoder is analyzed in detail, and the simulation sequence diagram and resource consumption are given. Secondly, according to the evolution of LDPC decoding algorithm, the probabilistic BP algorithm, logarithmic BP algorithm and normalized minimum sum algorithm are introduced, and their performance is simulated and compared. The decoding parameters such as the number of iterations and the quantization bit number of the initial value are simulated and the appropriate selection is made according to the simulation results. After that, the design idea of pipeline type decoder is put forward, and the algorithm of the normalized minimum sum decoding algorithm is given. Then, the structure and working principle of pipeline type decoder are introduced in detail. Two decoders are designed for regular and quasi-cyclic LDPC codes. The simulation results are given and the direction of further optimization is proposed. Finally, two groups of encoders and decoders are implemented on the FPGA experimental board. With the help of Matlab and serial port debugging assistant software, two sets of encoder and decoder system are formed to realize the work of encoding and decoding data with the help of serial port and computer. The performance of the encoder and decoder in practical application is also tested.
【學位授予單位】：哈爾濱工業(yè)大學
【學位級別】：碩士
【學位授予年份】：2014
【分類號】：TN911.2

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