本文選題：非結(jié)構(gòu)化　切入點：映射方法　出處：《西安電子科技大學(xué)》2014年碩士論文　論文類型：學(xué)位論文

【摘要】：低密度奇偶校驗(Low-Density Parity-Check,LDPC)碼具有優(yōu)異的性能,且譯碼涉及的數(shù)據(jù)運算簡單,該類碼字的FPGA實現(xiàn)已經(jīng)廣泛應(yīng)用于數(shù)字電視和通信等領(lǐng)域。非結(jié)構(gòu)化LDPC碼檢驗矩陣中非零元素的分布沒有任何規(guī)律,因而比結(jié)構(gòu)化LDPC碼的性能較好。但是,由于非結(jié)構(gòu)化碼字的校驗矩陣沒有循環(huán)結(jié)構(gòu)或者準循環(huán)結(jié)構(gòu),增加了非結(jié)構(gòu)碼字在邏輯設(shè)計與實現(xiàn)中的復(fù)雜度,同時矩陣中“1”不規(guī)律的分布增加了FPGA實現(xiàn)的邏輯設(shè)計難度。因此,本文重點研究了非結(jié)構(gòu)化碼字的邏輯設(shè)計與實現(xiàn),并提出一種基于行列置換的映射方法,以降低不規(guī)律度分布的影響,減少對碼字譯碼性能的影響,能夠有效地降低實現(xiàn)復(fù)雜度。本文的主要內(nèi)容如下:首先,介紹了兩種不同結(jié)構(gòu)的LDPC碼,詳細推導(dǎo)了幾種性能較好的譯碼算法,并針對同一組碼字給出了使用不同算法時的性能比較結(jié)果。然后,比較了不同結(jié)構(gòu)的碼字在邏輯設(shè)計與實現(xiàn)中的優(yōu)缺點,并且提出了一種基于行列置換的映射方法,以簡化非結(jié)構(gòu)化LDPC譯碼器的邏輯設(shè)計,有效降低FPGA實現(xiàn)的難度,還具體地分析了量化方案和譯碼算法中幾個關(guān)鍵參數(shù)對碼字性能的影響。最后,根據(jù)本文提出的用于簡化邏輯的映射方法,基于串行結(jié)構(gòu)設(shè)計并完成了非結(jié)構(gòu)化(548,274)LDPC譯碼器的邏輯設(shè)計,并進行綜合仿真和布局布線,可以較準確地譯出碼字。針對非結(jié)構(gòu)化LDPC譯碼器的FPGA設(shè)計與實現(xiàn),本文提出了一種并行設(shè)計思路以解決定點數(shù)尋址的沖突問題,從而獲得較高的數(shù)據(jù)處理速率。經(jīng)實際下板驗證,非結(jié)構(gòu)化(548,274)LDPC譯碼器可以正常工作,最高工作頻率為213.549MHz,經(jīng)計算數(shù)據(jù)吞吐率可達20Mbps左右。
[Abstract]:Low-Density Parity-Check-based LDPC (LDPC) codes with low density parity check have excellent performance, and the data operation involved in decoding is simple. The FPGA implementation of this kind of codewords has been widely used in digital television and communication fields. The distribution of nonzero elements in the unstructured LDPC code verification matrix has no rules, so it is better than the structured LDPC code. However, the performance of the unstructured LDPC code is better than that of the structured LDPC code. Because the check matrix of unstructured codewords has no cyclic structure or quasi-cyclic structure, the complexity of unstructured codewords in logic design and implementation is increased. At the same time, the irregular distribution of "1" in the matrix makes the logical design of FPGA more difficult. Therefore, this paper focuses on the logical design and implementation of unstructured codewords, and puts forward a mapping method based on column and column permutation. In order to reduce the influence of irregular degree distribution and the influence on codeword decoding performance, the implementation complexity can be reduced effectively. The main contents of this paper are as follows: firstly, two kinds of LDPC codes with different structures are introduced. Several decoding algorithms with good performance are deduced in detail, and the performance comparison results of different algorithms are given for the same group of codewords. Then, the advantages and disadvantages of different structure codewords in logic design and implementation are compared. A mapping method based on column and column permutation is proposed to simplify the logic design of unstructured LDPC decoder and reduce the difficulty of FPGA implementation. The effects of several key parameters in quantization scheme and decoding algorithm on codeword performance are also analyzed in detail. Finally, according to the mapping method proposed in this paper for simplifying logic, Based on the serial structure, the logic design of the unstructured LDPC decoder is designed and completed, and the integrated simulation and layout routing are carried out. The codewords can be translated more accurately. The FPGA design and implementation of the unstructured LDPC decoder is presented. In this paper, a parallel design method is proposed to solve the problem of addressing the fixed point number, so as to obtain a higher data processing rate. The unstructured LDPC decoder can work normally, which is verified by the actual downboard. The highest operating frequency is 213.549 MHz, and the calculated data throughput is about 20Mbps.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TN911.22;TN791

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