本文選題：非結(jié)構(gòu)化　切入點(diǎn)：映射方法　出處：《西安電子科技大學(xué)》2014年碩士論文　論文類(lèi)型：學(xué)位論文

【摘要】：低密度奇偶校驗(yàn)(Low-Density Parity-Check,LDPC)碼具有優(yōu)異的性能,且譯碼涉及的數(shù)據(jù)運(yùn)算簡(jiǎn)單,該類(lèi)碼字的FPGA實(shí)現(xiàn)已經(jīng)廣泛應(yīng)用于數(shù)字電視和通信等領(lǐng)域。非結(jié)構(gòu)化LDPC碼檢驗(yàn)矩陣中非零元素的分布沒(méi)有任何規(guī)律,因而比結(jié)構(gòu)化LDPC碼的性能較好。但是,由于非結(jié)構(gòu)化碼字的校驗(yàn)矩陣沒(méi)有循環(huán)結(jié)構(gòu)或者準(zhǔn)循環(huán)結(jié)構(gòu),增加了非結(jié)構(gòu)碼字在邏輯設(shè)計(jì)與實(shí)現(xiàn)中的復(fù)雜度,同時(shí)矩陣中“1”不規(guī)律的分布增加了FPGA實(shí)現(xiàn)的邏輯設(shè)計(jì)難度。因此,本文重點(diǎn)研究了非結(jié)構(gòu)化碼字的邏輯設(shè)計(jì)與實(shí)現(xiàn),并提出一種基于行列置換的映射方法,以降低不規(guī)律度分布的影響,減少對(duì)碼字譯碼性能的影響,能夠有效地降低實(shí)現(xiàn)復(fù)雜度。本文的主要內(nèi)容如下:首先,介紹了兩種不同結(jié)構(gòu)的LDPC碼,詳細(xì)推導(dǎo)了幾種性能較好的譯碼算法,并針對(duì)同一組碼字給出了使用不同算法時(shí)的性能比較結(jié)果。然后,比較了不同結(jié)構(gòu)的碼字在邏輯設(shè)計(jì)與實(shí)現(xiàn)中的優(yōu)缺點(diǎn),并且提出了一種基于行列置換的映射方法,以簡(jiǎn)化非結(jié)構(gòu)化LDPC譯碼器的邏輯設(shè)計(jì),有效降低FPGA實(shí)現(xiàn)的難度,還具體地分析了量化方案和譯碼算法中幾個(gè)關(guān)鍵參數(shù)對(duì)碼字性能的影響。最后,根據(jù)本文提出的用于簡(jiǎn)化邏輯的映射方法,基于串行結(jié)構(gòu)設(shè)計(jì)并完成了非結(jié)構(gòu)化(548,274)LDPC譯碼器的邏輯設(shè)計(jì),并進(jìn)行綜合仿真和布局布線(xiàn),可以較準(zhǔn)確地譯出碼字。針對(duì)非結(jié)構(gòu)化LDPC譯碼器的FPGA設(shè)計(jì)與實(shí)現(xiàn),本文提出了一種并行設(shè)計(jì)思路以解決定點(diǎn)數(shù)尋址的沖突問(wèn)題,從而獲得較高的數(shù)據(jù)處理速率。經(jīng)實(shí)際下板驗(yàn)證,非結(jié)構(gòu)化(548,274)LDPC譯碼器可以正常工作,最高工作頻率為213.549MHz,經(jīng)計(jì)算數(shù)據(jù)吞吐率可達(dá)20Mbps左右。
[Abstract]:Low-Density Parity-Check-based LDPC (LDPC) codes with low density parity check have excellent performance, and the data operation involved in decoding is simple. The FPGA implementation of this kind of codewords has been widely used in digital television and communication fields. The distribution of nonzero elements in the unstructured LDPC code verification matrix has no rules, so it is better than the structured LDPC code. However, the performance of the unstructured LDPC code is better than that of the structured LDPC code. Because the check matrix of unstructured codewords has no cyclic structure or quasi-cyclic structure, the complexity of unstructured codewords in logic design and implementation is increased. At the same time, the irregular distribution of "1" in the matrix makes the logical design of FPGA more difficult. Therefore, this paper focuses on the logical design and implementation of unstructured codewords, and puts forward a mapping method based on column and column permutation. In order to reduce the influence of irregular degree distribution and the influence on codeword decoding performance, the implementation complexity can be reduced effectively. The main contents of this paper are as follows: firstly, two kinds of LDPC codes with different structures are introduced. Several decoding algorithms with good performance are deduced in detail, and the performance comparison results of different algorithms are given for the same group of codewords. Then, the advantages and disadvantages of different structure codewords in logic design and implementation are compared. A mapping method based on column and column permutation is proposed to simplify the logic design of unstructured LDPC decoder and reduce the difficulty of FPGA implementation. The effects of several key parameters in quantization scheme and decoding algorithm on codeword performance are also analyzed in detail. Finally, according to the mapping method proposed in this paper for simplifying logic, Based on the serial structure, the logic design of the unstructured LDPC decoder is designed and completed, and the integrated simulation and layout routing are carried out. The codewords can be translated more accurately. The FPGA design and implementation of the unstructured LDPC decoder is presented. In this paper, a parallel design method is proposed to solve the problem of addressing the fixed point number, so as to obtain a higher data processing rate. The unstructured LDPC decoder can work normally, which is verified by the actual downboard. The highest operating frequency is 213.549 MHz, and the calculated data throughput is about 20Mbps.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類(lèi)號(hào)】：TN911.22;TN791

【相似文獻(xiàn)】

相關(guān)期刊論文 前10條

1 劉晴;;昆騰創(chuàng)新歸檔解決方案減輕了主存儲(chǔ)上非結(jié)構(gòu)化數(shù)據(jù)增長(zhǎng)的負(fù)擔(dān)[J];計(jì)算機(jī)與網(wǎng)絡(luò);2013年23期

2 繆紅;鐘華;龍昕;;元器件企業(yè)保護(hù)非結(jié)構(gòu)化大數(shù)據(jù)的研究[J];電子元件與材料;2014年06期

3 王曉麗;;基于網(wǎng)絡(luò)的中學(xué)非結(jié)構(gòu)化教育資源建設(shè)探析[J];中國(guó)教育信息化;2007年08期

4 ToddMatsler;;深耕大數(shù)據(jù) 助力平安城市智慧轉(zhuǎn)型[J];中國(guó)信息界;2013年12期

5 經(jīng)有國(guó);但斌;張旭梅;郭鋼;;基于本體的非結(jié)構(gòu)化客戶(hù)需求智能解析方法[J];計(jì)算機(jī)集成制造系統(tǒng);2010年05期

6 張廣泉;非結(jié)構(gòu)化程序流程圖及其等價(jià)變換[J];重慶師范學(xué)院學(xué)報(bào)(自然科學(xué)版);1993年03期

7 王曉波;;非結(jié)構(gòu)化數(shù)據(jù)采集和檢索技術(shù)的研究與實(shí)現(xiàn)[J];中國(guó)內(nèi)部審計(jì);2014年07期

8 黃遠(yuǎn)鳴;;一種非結(jié)構(gòu)化數(shù)據(jù)的多牽度分配存取實(shí)現(xiàn)方法[J];科技通報(bào);2014年08期

9 劉威,武家春,廖建新,丁軼;非結(jié)構(gòu)化補(bǔ)充業(yè)務(wù)數(shù)據(jù)中心的設(shè)計(jì)與實(shí)現(xiàn)[J];計(jì)算機(jī)工程與應(yīng)用;2005年10期

10 羅文華;;非結(jié)構(gòu)化數(shù)據(jù)處理分析在電子數(shù)據(jù)取證中的應(yīng)用[J];警察技術(shù);2010年03期

相關(guān)會(huì)議論文 前10條

1 祝世京;陳s，

本文編號(hào)：1630736