發(fā)布時間：2018-03-15 05:37

  本文選題：脈沖壓縮　切入點：數(shù)字下變頻　出處：《哈爾濱工程大學》2014年碩士論文　論文類型：學位論文

【摘要】：脈沖壓縮技術能有效的解決目標的探測距離、距離分辨力和速度分辨力矛盾的問題,而被廣泛的應用于現(xiàn)代雷達信號處理中。隨著FPGA和CPLD器件的不斷發(fā)展,其數(shù)字信號處理性能的不斷提升,利用FPGA來實現(xiàn)雷達的數(shù)字脈沖壓縮成為一種主流趨勢。本文首先對脈沖壓縮系統(tǒng)的發(fā)展及現(xiàn)狀進行了分析,介紹了脈沖壓縮系統(tǒng)的相關原理,其主要包括數(shù)字下變頻技術、線性調頻信號的脈沖壓縮技術和距離旁瓣的抑制方法;對于線性調頻信號、非線性調頻信號和相位編碼信號進行了優(yōu)缺點對比,根據(jù)實際需要選用線性調頻信號實現(xiàn)脈沖壓縮。隨后對比分析了兩種實現(xiàn)數(shù)字脈沖壓縮的方法,選用頻域的脈沖壓縮方案實現(xiàn)脈沖壓縮系統(tǒng),通過理論分析選定合適的線性調頻信號參數(shù),采用MATLAB仿真軟件進行了系統(tǒng)仿真驗證,并分析了噪聲對脈壓系統(tǒng)的影響。對于硬件實現(xiàn)部分,采用結構化的設計思想對脈壓系統(tǒng)進行功能模塊的劃分,通過調用FPGA IP core和VHDL語言編程設計模塊的方法實現(xiàn)脈沖壓縮系統(tǒng),對于硬件實現(xiàn)系統(tǒng)的方案進行了詳細的介紹。最后通過MATLAB與Quartus Ⅱ聯(lián)合仿真的方法對系統(tǒng)進行了功能測試。本文設計的數(shù)字脈沖壓縮系統(tǒng)已經(jīng)在EP2S60 ( EP2S60F672C5ES )平臺上獲得實現(xiàn),通過實驗測試,實際脈壓系統(tǒng)的脈壓結果良好,性能指標達到了設計要求。
[Abstract]:Pulse compression technology can effectively solve the problem of target detection distance, range resolution and velocity resolution, which is widely used in modern radar signal processing. With the development of FPGA and CPLD devices, With the improvement of digital signal processing performance, it has become a mainstream trend to use FPGA to realize the digital pulse compression of radar. Firstly, the development and current situation of pulse compression system are analyzed, and the related principle of pulse compression system is introduced. It mainly includes digital down-conversion technology, pulse compression technology of linear frequency modulation signal and suppression method of range sidelobe, and compares advantages and disadvantages of linear frequency modulation signal, nonlinear frequency modulation signal and phase coded signal. According to the actual needs, the linear frequency modulation signal is selected to realize pulse compression. Then, two methods to realize digital pulse compression are compared and analyzed. The pulse compression system is realized by using frequency domain pulse compression scheme. Through theoretical analysis, the suitable parameters of LFM signal are selected, the system simulation is verified by MATLAB software, and the influence of noise on pulse compression system is analyzed. The function modules of pulse compression system are divided by structured design idea, and the pulse compression system is realized by calling FPGA IP core and VHDL language programming design module. The hardware implementation scheme of the system is introduced in detail. Finally, the function of the system is tested by the method of MATLAB and Quartus 鈪，

本文編號：1614684