本文選題：現(xiàn)場(chǎng)可編程邏輯門陣列　切入點(diǎn)：動(dòng)目標(biāo)顯示　出處：《西安電子科技大學(xué)》2014年碩士論文　論文類型：學(xué)位論文

【摘要】：雷達(dá)工作的電磁環(huán)境比較復(fù)雜,經(jīng)常受到各種雜波干擾。為了提取出所需目標(biāo),需要對(duì)雜波進(jìn)行抑制。在工程實(shí)現(xiàn)中,一般采用動(dòng)目標(biāo)顯示、動(dòng)目標(biāo)檢測(cè)、恒虛警和雜波圖等方法來(lái)實(shí)現(xiàn)�，F(xiàn)場(chǎng)可編程邏輯門陣列(FPGA)處理速率高,帶寬大,配合DDR3強(qiáng)大的緩存能力,可以實(shí)現(xiàn)對(duì)雷達(dá)回波數(shù)據(jù)的高速處理。本論文對(duì)運(yùn)動(dòng)目標(biāo)檢測(cè)的相關(guān)算法進(jìn)行了仿真分析,給出了工程實(shí)現(xiàn)方式,論文主要從以下幾點(diǎn)展開的:1.從鋸齒線性調(diào)頻連續(xù)波雷達(dá)的工作原理出發(fā),仿真了抑制固定地物雜波的動(dòng)目標(biāo)顯示技術(shù)。比較了動(dòng)目標(biāo)顯示的不同實(shí)現(xiàn)方式和優(yōu)缺點(diǎn);針對(duì)動(dòng)目標(biāo)檢測(cè)技術(shù),給出兩種多普勒濾波器組的實(shí)現(xiàn)方式;針對(duì)雷達(dá)信號(hào)檢測(cè)時(shí)的恒虛警檢測(cè)處理,給出了四種恒虛警電路的實(shí)現(xiàn)方式;利用零通道幅度信息,建立了零速雜波圖,并給出了超雜波檢測(cè)方法;針對(duì)多普勒聚心技術(shù),給出了工程實(shí)現(xiàn)方式。2.完成了硬件平臺(tái)的設(shè)計(jì)。給出了信號(hào)處理板的結(jié)構(gòu)框圖,該處理板板間和板內(nèi)數(shù)據(jù)傳輸帶寬大,可以滿足內(nèi)外接口需求。給出了該硬件平臺(tái)的FPGA資源,該FPGA集成度高,功耗低,并且能夠反復(fù)編程;內(nèi)部流水處理,能夠大大降低處理延時(shí),提高數(shù)據(jù)處理速度;有著更多的邏輯資源、乘法器和控制器等硬件資源,可以快速的進(jìn)行信號(hào)處理和邏輯控制。FPGA內(nèi)部存儲(chǔ)空間有限,在進(jìn)行數(shù)據(jù)處理的過(guò)程中需要緩存大量的數(shù)據(jù)。DDR3由于具有高速、大容量存儲(chǔ)等優(yōu)點(diǎn),可以很好的與FPGA配合來(lái)實(shí)現(xiàn)數(shù)據(jù)緩存的功能。3.給出了雷達(dá)信號(hào)處理的運(yùn)動(dòng)目標(biāo)檢測(cè)方案。設(shè)計(jì)了動(dòng)目標(biāo)顯示、動(dòng)目標(biāo)檢測(cè)、恒虛警、超雜波檢測(cè)和多普勒聚心等功能的框圖。在數(shù)據(jù)緩存控制時(shí),加入數(shù)據(jù)重排的功能。通過(guò)對(duì)DDR3地址位的控制,配合FPGA內(nèi)部的緩存RAM,可以根據(jù)后級(jí)處理的需求,實(shí)現(xiàn)數(shù)據(jù)的重排,極大的縮短了信號(hào)處理時(shí)間。4.給出實(shí)測(cè)數(shù)據(jù)的處理結(jié)果,驗(yàn)證了FPGA所實(shí)現(xiàn)功能的正確性。并對(duì)本文中存在的一些問(wèn)題進(jìn)行總結(jié),給出了一些改進(jìn)性措施。
[Abstract]:The electromagnetic environment of radar work is complex, and it is often disturbed by various clutter. In order to extract the desired target, it is necessary to suppress the clutter. In engineering implementation, moving target display is generally used to detect moving target. Field Programmable Logic Gate Array (FPGA) has high processing speed, large bandwidth and strong buffer capacity with DDR3. The high speed processing of radar echo data can be realized. In this paper, the related algorithms of moving target detection are simulated and analyzed, and the engineering realization method is given. This paper mainly focuses on the following points: 1. Based on the working principle of serrated LFM continuous wave radar, this paper simulates the display technology of moving target for suppressing clutter of fixed ground object, and compares the different realization methods, advantages and disadvantages of moving target display; Aiming at moving target detection technology, two kinds of Doppler filter banks are given, four kinds of CFAR circuits are given for radar signal detection and processing, and zero channel amplitude information is used. The zero-velocity clutter diagram is established, and the detection method of super-clutter is given, and the engineering realization mode .2. the design of hardware platform and the structure block diagram of the signal processing board are given, according to the Doppler centroid technology, the design of the hardware platform is completed, and the structure of the signal processing board is given. The FPGA resource of the hardware platform is given, which has the advantages of high integration, low power consumption, and can be programmed repeatedly. Can greatly reduce processing delay, improve data processing speed, with more logical resources, multiplier and controller and other hardware resources, can quickly carry out signal processing and logic control. FPGA internal storage space is limited. In the process of data processing, it is necessary to cache a large amount of data. DDR3 has the advantages of high speed, large capacity storage, etc. It can work well with FPGA to realize the function of data cache. 3. The scheme of moving target detection for radar signal processing is given. The moving target display, moving target detection, constant false alarm rate are designed. In the data cache control, the function of data rearrangement is added. Through the control of DDR3 address bit and the buffer within FPGA, the data rearrangement can be realized according to the demand of post-processing. The signal processing time is greatly shortened. 4. The processing results of the measured data are given, and the correctness of the functions realized by FPGA is verified. Some problems in this paper are summarized, and some improvement measures are given.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：TN957.51

【參考文獻(xiàn)】

相關(guān)期刊論文 前2條

1 孫延坤;陳興波;曹晨;李廣軍;;基于MSK-LFM的PD雷達(dá)信號(hào)處理仿真[J];中國(guó)電子科學(xué)研究院學(xué)報(bào);2012年04期

2 簡(jiǎn)育華;李軍輝;徐飛;雷剛;;基于DDR3的數(shù)據(jù)重排設(shè)計(jì)[J];火控雷達(dá)技術(shù);2013年02期

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本文編號(hào)：1579446