本文選題：極坐標(biāo)發(fā)射機(jī)　切入點(diǎn)：寬帶相調(diào)制　出處：《電子科技大學(xué)》2014年碩士論文　論文類型：學(xué)位論文

【摘要】：極坐標(biāo)發(fā)射機(jī)是一種理論上可以同時(shí)滿足高效率和高線性度指標(biāo)的發(fā)射機(jī)結(jié)構(gòu)。而由于現(xiàn)代通信中基帶數(shù)據(jù)傳輸?shù)乃俾试絹?lái)越高,傳統(tǒng)應(yīng)用于極坐標(biāo)發(fā)射機(jī)中的基于鎖相環(huán)的相位調(diào)制結(jié)構(gòu)已經(jīng)無(wú)法滿足系統(tǒng)對(duì)于帶寬的要求,因此新型的寬帶相位調(diào)制結(jié)構(gòu)是本文研究的重點(diǎn)。本文在基于對(duì)數(shù)字時(shí)鐘信號(hào)的新型定義下,研究了一種寬帶相位調(diào)制系統(tǒng),即基于小數(shù)分頻數(shù)字分頻器的頻率合成器。本文的主要工作和創(chuàng)新之處如下文所示：1.定義了新型的數(shù)字時(shí)鐘信號(hào)。通用的數(shù)字時(shí)鐘信號(hào)是單一周期的無(wú)限次重復(fù),而在本文定義的數(shù)字時(shí)鐘信號(hào)是由多個(gè)周期不同的基本信號(hào)在長(zhǎng)時(shí)間的平均得到的平均周期。采用如上定義的數(shù)字時(shí)鐘信號(hào)比起通用時(shí)鐘信號(hào)來(lái)說(shuō),其硬件電路實(shí)現(xiàn)將會(huì)簡(jiǎn)單,對(duì)于大規(guī)模集成電路會(huì)是一個(gè)好處。2.研究了基于小數(shù)分頻數(shù)字分頻器的頻率合成器。這種頻率合成器的輸出時(shí)鐘信號(hào)是定義了的新型數(shù)字時(shí)鐘信號(hào),即其輸出頻率是若干個(gè)基本頻率的綜合而成,而不是傳統(tǒng)意義中的單一頻率；除此之外,其輸出信號(hào)是方波形式,有益于數(shù)字電路的集成。3.本文研究的基于小數(shù)分頻數(shù)字分頻器的頻率合成器的寬帶相位調(diào)制系統(tǒng)是一個(gè)開(kāi)環(huán)的相位調(diào)制系統(tǒng)。因?yàn)樵撓辔徽{(diào)制系統(tǒng)是開(kāi)環(huán)系統(tǒng),所以基帶數(shù)據(jù)的速率不會(huì)受到像鎖相環(huán)式的相位調(diào)制系統(tǒng)中的閉環(huán)帶寬影響；因此對(duì)于寬帶相位信號(hào)來(lái)說(shuō),該方案是可行的。4.研究了寬帶相位調(diào)制系統(tǒng)中的重要模塊,即無(wú)雜散量化模塊。該模塊的設(shè)計(jì)采用了統(tǒng)計(jì)的思想,將確定性的雜散信號(hào)轉(zhuǎn)化為不確定的雜散信號(hào),使其功率譜的幅值小于輸出信號(hào)的噪底,在這種情況下可以保證輸出信號(hào)的功率譜輸出無(wú)雜散。除此之外,在對(duì)連續(xù)量化器的設(shè)計(jì)之初就考慮了非線性電路對(duì)于輸出信號(hào)頻譜的影響,因此連續(xù)量化器輸出的量化噪聲的多次方功率譜均無(wú)雜散信號(hào)。硬件測(cè)試結(jié)果表明在該系統(tǒng)的參考輸入時(shí)鐘信號(hào)的頻率是1GHz時(shí),基帶相位信號(hào)的傳輸速率可以達(dá)到20Mbps,而其EVM可以保持在4.54%。而其在不同參考時(shí)鐘信號(hào)的頻率下其EVM是不同的結(jié)果,理論上來(lái)講,參考輸入時(shí)鐘信號(hào)的頻率越高,EVM的效果可以更好。因此基于小數(shù)分頻數(shù)字分頻器的頻率合成器可以作為寬帶相位調(diào)制器使用。
[Abstract]:Polar coordinate transmitter is a transmitter structure which can satisfy both high efficiency and high linearity in theory. However, because of the increasing rate of baseband data transmission in modern communication, The traditional phase-locked loop (PLL) based phase modulation structure used in polar transmitters can no longer meet the bandwidth requirements of the system. Therefore, a novel wideband phase modulation structure is the focus of this paper. Based on the new definition of digital clock signal, a wideband phase modulation system is studied in this paper. The main work and innovation of this paper are as follows: 1. A new digital clock signal is defined. The universal digital clock signal is an infinite repetition of a single period. The digital clock signal defined in this paper is the average period obtained from the average period of several different basic signals over a long period of time. Using the digital clock signal defined above, the hardware implementation of the digital clock signal will be simpler than that of the universal clock signal. The frequency synthesizer based on fractional frequency divider is studied. The output clock signal of this frequency synthesizer is a new digital clock signal defined. That is, its output frequency is a combination of several basic frequencies, rather than a single frequency in the traditional sense; in addition, its output signal is in the form of square waves. The broadband phase modulation system based on frequency synthesizer based on fractional frequency divider is an open-loop phase modulation system, because the phase modulation system is an open-loop system. Therefore, the rate of baseband data will not be affected by the closed-loop bandwidth in phase-locked loop (PLL) phase modulation system; therefore, this scheme is feasible for wideband phase signals. 4. The important modules in wideband phase modulation system are studied. The design of the module adopts the idea of statistics, which converts deterministic stray signal into uncertain spurious signal, and makes the amplitude of power spectrum smaller than the noise bottom of output signal. In this case, the power spectrum output of the output signal can be guaranteed without stray. In addition, the influence of nonlinear circuit on the output signal spectrum is considered at the beginning of the design of the continuous quantizer. Therefore, there is no stray signal in multiple square power spectrum of quantization noise output by the continuous quantizer. The hardware test results show that when the frequency of the reference clock signal of the system is 1GHz, The transmission rate of the baseband phase signal can reach 20 Mbpss, and its EVM can be kept at 4.54.The EVM of the baseband phase signal is different at different frequency of the reference clock signal, theoretically speaking, The higher the frequency of the reference clock signal, the better the effect of EVM. Therefore, the frequency synthesizer based on the fractional digital frequency divider can be used as the wideband phase modulator.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：TN830

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