發(fā)布時(shí)間：2018-03-05 06:05

  本文選題：無線通信　切入點(diǎn)：信道編碼　出處：《西安電子科技大學(xué)》2014年碩士論文　論文類型：學(xué)位論文

【摘要】：近年來,無線通信技術(shù)得到了迅猛發(fā)展。無線通信的信道同有線通信相比,存在更多的干擾和更強(qiáng)的衰落,這無疑降低了無線通信的可靠性。為了提高無線通信系統(tǒng)的可靠性,降低誤碼率,通常采用信道編碼技術(shù)。信道編碼技術(shù)已經(jīng)成為無線通信中十分重要的一部分。Turbo乘積碼是一種新型、高效的信道編碼技術(shù),其采用線性分組碼作為子碼,譯碼過程采用軟輸入軟輸出的譯碼算法,使得其譯碼過程相對(duì)Turbo碼要簡(jiǎn)單許多,而譯碼性能上又十分可靠。本文首先介紹了信道編碼的發(fā)展歷史,和TPC編譯碼的基本原理,著重介紹了基于ChaseII譯碼算法的軟輸入軟輸出迭代譯碼原理。接下來分析了影響TPC譯碼性能的一些因素,并在Matlab軟件環(huán)境下進(jìn)行了仿真,這些因素將決定設(shè)計(jì)譯碼器時(shí)的參數(shù)選取。然后分析了ChaseII譯碼算法的簡(jiǎn)化方法,這些簡(jiǎn)化條件將使譯碼器的復(fù)雜度降低。然后,設(shè)計(jì)了串行和并行兩種迭代方式的譯碼器,并且根據(jù)性能仿真結(jié)果比較了二者的性能差異。最后,使用Verilog語(yǔ)言完成了TPC編譯碼器的FPGA實(shí)現(xiàn)。其中編碼器較為簡(jiǎn)單,串行和并行迭代譯碼器較為復(fù)雜。在QuartusII環(huán)境下完成編譯碼器的設(shè)計(jì),著重比較了兩種不同迭代方式譯碼器的譯碼延時(shí)和資源占用情況。使用ModelSim軟件觀察譯碼輸出波形圖,并將譯碼輸出結(jié)果與發(fā)送的原始比特進(jìn)行對(duì)照,驗(yàn)證譯碼器的正確性。
[Abstract]:In recent years, wireless communication technology has developed rapidly. Compared with wired communication, the channel of wireless communication has more interference and stronger fading, which undoubtedly reduces the reliability of wireless communication. To reduce the bit error rate (BER), channel coding technology is usually adopted, which has become a very important part of wireless communication. Turbo product code is a new and efficient channel coding technique, which uses linear block codes as subcodes. The decoding process adopts soft input and soft output decoding algorithm, which makes the decoding process much simpler than Turbo code, and the decoding performance is very reliable. Firstly, this paper introduces the history of channel coding and the basic principle of TPC coding and decoding. The principle of soft input and soft output iterative decoding based on ChaseII decoding algorithm is introduced emphatically. Then, some factors that affect the decoding performance of TPC are analyzed, and the simulation is carried out under the environment of Matlab software. These factors will determine the selection of parameters when designing the decoder. Then, the simplified method of ChaseII decoding algorithm is analyzed, which will reduce the complexity of the decoder. Then, the serial and parallel iterative decoders are designed. Finally, the FPGA implementation of TPC codec is implemented with Verilog language. The encoder is relatively simple. The serial and parallel iterative decoders are more complicated. The decoder is designed in QuartusII environment, and the decoding delay and resource occupation of two different iterative decoders are compared. The output waveform diagram of decoding is observed by ModelSim software. The output of the decoder is compared with the original bit to verify the correctness of the decoder.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：TN915.04;TN914

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本文編號(hào)：1569029