本文關(guān)鍵詞： 低量化比特 數(shù)字接收機(jī) 相位估計(jì) 自動增益控制 dither　出處：《電子科技大學(xué)》2014年碩士論文　論文類型：學(xué)位論文

【摘要】：數(shù)字信號處理技術(shù)(DSP)是現(xiàn)代數(shù)字通信的核心,數(shù)字解調(diào)器比模擬解調(diào)器具有更高精度、更高的靈活性和穩(wěn)定性,因此得到廣泛的應(yīng)用。但是隨著數(shù)字信號的發(fā)展,數(shù)字模擬轉(zhuǎn)換器(ADC)逐漸成為數(shù)字通信的限制因素。采樣速率達(dá)到數(shù)Gsps的ADC并不多見,并且高速率且高精度的ADC的功耗非常大,不適合用于通信系統(tǒng)中的移動設(shè)備。然而經(jīng)過研究表明,低精度量化是一種有效的解決方案。低精度量化尤其是1bit量化在超寬帶通信中已經(jīng)有著很多的研究和應(yīng)用,但是在非超寬帶的通信系統(tǒng)的研究中比較少見。本論文研究的主要內(nèi)容是低精度的ADC在數(shù)字通信系統(tǒng)中的應(yīng)用以及如何利用極少的量化比特(通常為1~4bit)實(shí)現(xiàn)數(shù)字信號的自動增益控制和載波相位偏移恢復(fù)。第二章對數(shù)字接收機(jī)受到低量化比特的影響進(jìn)行了分析,主要是針對2-4比特下QPSK或16QAM的數(shù)字接收機(jī),也包含了在系統(tǒng)有緩慢衰減,相位偏差或者符號定時(shí)誤差,仿真結(jié)果顯示當(dāng)量化器的量化步長設(shè)置合理之時(shí)系統(tǒng)的性能是可以接受的。本文同時(shí)也對于數(shù)字接收機(jī)中的自動增益控制和相位估計(jì)進(jìn)行的分析。第三章主要研究了QPSK數(shù)字接收機(jī)的中的相位估計(jì)在低量化比特條件下的影響。本章首先對不同相位估計(jì)算法在高量化噪聲下的影響,同時(shí)本文給出了一中實(shí)用的相位估計(jì)器。自動增益控制是接收機(jī)中的一個(gè)重要部分,第四章首先對不同的自動增益控制算法進(jìn)行了討論和分析,然后通過對傳統(tǒng)的自動增益控制進(jìn)行了仿真并且分析了低量化比特下的自動增益控制的性能改變。Dither在很多領(lǐng)域中有著非常重要的作用,在模數(shù)轉(zhuǎn)換中加入合適的dither信號可以提高有效精度。本文對ADC中的dither進(jìn)行了討論,同時(shí)也對相位估計(jì)中的dither進(jìn)行了討論。
[Abstract]:Digital signal processing (DSP) is the core of modern digital communication. Digital demodulator has higher precision, higher flexibility and stability than analog demodulator, so it is widely used. Digital to analog converter (DAC) is becoming the limiting factor of digital communication. ADC with sampling rate up to the number of Gsps is rare, and the power consumption of high speed and high precision ADC is very large. However, low precision quantization is an effective solution. Low precision quantization, especially 1bit quantization, has been studied and applied in UWB communication. However, the research of non-UWB communication system is rare. The main content of this thesis is the application of low-precision ADC in digital communication system and how to realize digital by using very few quantization bits (usually 1bit). The signal automatic gain control and carrier phase offset recovery. Chapter 2 analyzes the influence of low quantization bits on the digital receiver. Digital receivers for QPSK or 16QAM at 2-4 bits also include slow attenuation, phase deviations or symbol timing errors. The simulation results show that the performance of the system is acceptable when the quantizer's quantization step size is reasonable. This paper also analyzes the automatic gain control and phase estimation in the digital receiver. The influence of phase estimation in QPSK digital receiver under low quantization bit condition is investigated. Firstly, the effect of different phase estimation algorithms on high quantization noise is discussed. At the same time, a practical phase estimator is given in this paper. Automatic gain control is an important part of the receiver. Chapter 4th discusses and analyzes different automatic gain control algorithms. Then the traditional AGC is simulated and the performance change of AGC under low quantization bit is analyzed. Dither plays a very important role in many fields. The effective precision can be improved by adding appropriate dither signal to the analog-to-digital conversion. The dither in ADC and the dither in phase estimation are discussed in this paper.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TN914.3

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本文編號：1547406