本文關(guān)鍵詞： 抗混疊 數(shù)字信道化接收機(jī) 參數(shù)測(cè)量 FPGA DDR3 RapidIO　出處：《南京理工大學(xué)》2014年碩士論文　論文類型：學(xué)位論文

【摘要】：近年來(lái),隨著無(wú)線電技術(shù)的迅猛發(fā)展,電子對(duì)抗的頻帶越來(lái)越寬,形式越來(lái)越復(fù)雜多變,傳統(tǒng)的電子偵察接收機(jī)已經(jīng)遠(yuǎn)遠(yuǎn)不能滿足要求。于是,基于軟件無(wú)線電構(gòu)想的大動(dòng)態(tài)范圍、寬瞬時(shí)接收帶寬、高靈敏度、高分辨率、多信號(hào)處理能力的數(shù)字信道化接收機(jī)應(yīng)運(yùn)而生。本文的主要研究?jī)?nèi)容有： 分析了數(shù)字信道化的基本理論,針對(duì)信道化接收機(jī)相鄰信道交界處有混疊的問(wèn)題,推導(dǎo)了抗混疊信道化接收機(jī)結(jié)構(gòu),仿真試驗(yàn)和數(shù)據(jù)驗(yàn)證了該結(jié)構(gòu)的可行性。 研究了通信信號(hào)的檢測(cè)和參數(shù)估計(jì)的問(wèn)題。為了提高檢測(cè)性能,提出了適應(yīng)本工程的恒虛警檢測(cè)方案。深入研究了通信信號(hào)測(cè)頻算法,推導(dǎo)了基于測(cè)相的頻率估計(jì)算法,并使用CORDIC算法優(yōu)化結(jié)構(gòu),仿真試驗(yàn)表明,該算法能夠達(dá)到課題的性能指標(biāo)。 探索了通信信號(hào)信道化檢測(cè)及其參數(shù)估計(jì)的FPGA實(shí)現(xiàn)方法,詳細(xì)分析了實(shí)現(xiàn)過(guò)程中遇到的問(wèn)題并給出了解決方案。詳細(xì)介紹了本工程中各模塊的實(shí)現(xiàn)結(jié)構(gòu),為工程實(shí)驗(yàn)結(jié)果再現(xiàn)提供便利。 實(shí)現(xiàn)了FPGA與DSP高速互連通信。一方面使用DDR3實(shí)現(xiàn)了高速率數(shù)據(jù)的存儲(chǔ)和讀取,研究了多種DDR3的控制方法,并對(duì)這些方法進(jìn)行了比較和分析,提出了一些使用建議。另一方面使用RapidIO實(shí)現(xiàn)了FPGA與DSP高速數(shù)據(jù)傳輸,分析了IP核RapidIOv5.6的使用方法并在硬件上進(jìn)行了實(shí)驗(yàn),實(shí)驗(yàn)表明單路傳輸速率可以達(dá)到3.125Gbaud。
[Abstract]:In recent years, with the rapid development of radio technology, the frequency band of electronic countermeasure is becoming wider and wider, the form is more and more complex and changeable, the traditional electronic reconnaissance receiver is far from meeting the requirements. The digital channelized receiver based on the concept of software radio has the following characteristics: large dynamic range, wide instantaneous receiving bandwidth, high sensitivity, high resolution and multi-signal processing capability. The main contents of this paper are as follows:. The basic theory of digital channelization is analyzed and the structure of anti-aliasing channelized receiver is deduced aiming at the problem of aliasing at the junction of adjacent channels of channelized receiver. The feasibility of the structure is verified by simulation and data. The problem of communication signal detection and parameter estimation is studied. In order to improve the detection performance, a CFAR detection scheme adapted to this project is proposed. The frequency measurement algorithm of communication signal is studied in depth, and the frequency estimation algorithm based on phase measurement is derived. The CORDIC algorithm is used to optimize the structure and the simulation results show that the algorithm can achieve the performance index of the project. This paper explores the FPGA implementation method for channelization detection and parameter estimation of communication signals, analyzes the problems encountered in the process of implementation and gives the solutions. The implementation structure of each module in this project is introduced in detail. It is convenient to reproduce the results of engineering experiments. On the one hand, we use DDR3 to realize the storage and reading of high rate data, and study the control methods of various DDR3, and compare and analyze these methods. On the other hand, using RapidIO to realize high speed data transmission between FPGA and DSP, the use method of IP core RapidIOv5.6 is analyzed and the experiment on hardware is carried out. The experiment shows that the single transmission rate can reach 3.125 Gbaud.
【學(xué)位授予單位】：南京理工大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：TN911.23

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本文編號(hào)：1546540