發(fā)布時間：2018-02-27 18:31

  本文關(guān)鍵詞： EPoC系統(tǒng) 數(shù)字中頻技術(shù) 多相濾波 并行DDS頻率合成技術(shù)　出處：《電子科技大學》2014年碩士論文　論文類型：學位論文

【摘要】：作為我國網(wǎng)絡(luò)設(shè)施建設(shè)發(fā)展的關(guān)鍵基礎(chǔ),加快發(fā)展電信網(wǎng)、廣播電視網(wǎng)、互聯(lián)網(wǎng)三網(wǎng)融合至關(guān)重要。三網(wǎng)融合中,為了滿足支持多業(yè)務(wù)共存、家庭內(nèi)部接入多終端、高帶寬中強QoS等需求,EPoC技術(shù)作為下一代廣播電視網(wǎng)的發(fā)展方向,實現(xiàn)了寬帶化改造現(xiàn)有的光纖同軸混合網(wǎng),來構(gòu)建高速雙向接入網(wǎng)。為滿足EPoC系統(tǒng)的寬帶高速傳輸需求,論文研究了10Gbps EPoC數(shù)字中頻關(guān)鍵技術(shù)。論文中10Gbps EPoC數(shù)字中頻設(shè)計,采用了多相濾波技術(shù)及并行DDS頻率合成器技術(shù),論文對這兩種關(guān)鍵技術(shù)的設(shè)計、仿真與實現(xiàn)進行了仔細研究與分析。論文完成的主要工作如下:(1)論文結(jié)合數(shù)字中頻的多相濾波技術(shù)研究,對適用于EPoC樣機系統(tǒng)的數(shù)字中頻的數(shù)字變頻器進行算法設(shè)計和實現(xiàn)�？偨Y(jié)出支持48MHz及192MHz兩種信號帶寬模式的數(shù)字變頻器設(shè)計,設(shè)計仿真的浮點以及定點鏈路發(fā)送接收單邊EVM均小于0.5%,并在FPGA上加以實現(xiàn)。論文對數(shù)字中頻載波模塊中的并行DDS頻率合成器進行算法設(shè)計,仿真中DDS支持頻段5MHz~1536MHz,且雜散大于60dB,并在FPGA上實現(xiàn)了該模塊功能。(2)論文根據(jù)EPoC樣機系統(tǒng)設(shè)計需求,總結(jié)出相關(guān)數(shù)據(jù)接口設(shè)計。在FPGA上實現(xiàn)了與基帶板交互的數(shù)據(jù)接口,與ADC芯片、DAC芯片交互接口以及配置板內(nèi)板間各個參數(shù)的SPI接口。與基帶板交互數(shù)據(jù)接口達到了系統(tǒng)樣機的10Gbps速率傳輸要求。(3)對數(shù)字中頻射頻前端系統(tǒng)進行了代碼集成,搭建測試平臺,對EPoC射頻前端樣機進行測試與分析。測試結(jié)果表明,各項指標均達到了EPoC射頻前端樣機的設(shè)計需求,樣機發(fā)送和接收總體EVM指標小于1%,并且系統(tǒng)樣機的頻帶利用率可達8.6bps/Hz。以上結(jié)論驗證了論文設(shè)計的數(shù)字中頻信號處理系統(tǒng)在EPoC射頻前端樣機中滿足系統(tǒng)的高速率傳輸要求,為EPoC系統(tǒng)在我國的發(fā)展做出了貢獻。
[Abstract]:As the key foundation of the construction and development of network facilities in China, it is very important to accelerate the development of telecommunication network, radio and television network and Internet triple network convergence. As the development direction of the next generation radio and television network, EPoC technology with high bandwidth, such as strong QoS and so on, realizes the broadband transformation of the existing optical fiber coaxial hybrid network to construct a high-speed two-way access network. In this paper, the key technology of 10Gbps EPoC digital intermediate frequency is studied. In this paper, the design of 10Gbps EPoC digital intermediate frequency is carried out, and the polyphase filter and parallel DDS frequency synthesizer are adopted. The two key technologies are designed in this paper. The main work of this paper is as follows: 1) the thesis combines with the polyphase filtering technology of digital intermediate frequency. The algorithm design and implementation of digital intermediate frequency converter suitable for EPoC prototype system are presented. The design of digital frequency converter which supports two signal bandwidth modes of 48MHz and 192MHz is summarized. In this paper, the floating-point and fixed-point link sending and receiving one-sided EVM are all less than 0.5 and implemented on FPGA. The parallel DDS frequency synthesizer in the digital if carrier module is designed in this paper. In the simulation, the DDS supports the frequency band of 5MHz / 1536MHz, and the stray is greater than 60dB, and realizes the function of the module on FPGA. (2) according to the design requirements of the EPoC prototype system, the paper summarizes the design of the related data interface, and realizes the data interface with the baseband board on the FPGA. The interface with the ADC chip and the SPI interface of the parameters between the inner board and the baseband board. The data interface with the baseband board meets the 10Gbps rate transmission requirement of the system prototype, and the code integration of the digital if RF front-end system is carried out. The test platform is built to test and analyze the EPoC RF front-end prototype. The test results show that all the indexes meet the design requirements of the EPoC RF front-end prototype. The overall EVM index of the prototype is less than 1, and the frequency band efficiency of the prototype can reach 8.6 BP / Hz. the above conclusion verifies that the digital if signal processing system designed in this paper can meet the requirement of high rate transmission in the EPoC RF front-end prototype. It has contributed to the development of EPoC system in our country.
【學位授予單位】：電子科技大學
【學位級別】：碩士
【學位授予年份】：2014
【分類號】：TN948.3

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本文編號：1543850