本文關(guān)鍵詞： TMS320C6678 并行處理 FFT 合成孔徑雷達(dá)　出處：《北京理工大學(xué)》2014年碩士論文　論文類型：學(xué)位論文

【摘要】：隨著雷達(dá)成像技術(shù)的不斷發(fā)展，對(duì)成像范圍、成像精度和處理實(shí)時(shí)性的要求越來(lái)越高，這就提出了對(duì)更大數(shù)據(jù)量、運(yùn)算量和成像速度的需求，一般情況下的采用單核DSP完成計(jì)算已經(jīng)不能滿足這方面需求的變化，多核DSP并行處理成為發(fā)展的趨勢(shì)，業(yè)內(nèi)關(guān)于TMS320C6678多核DSP芯片的研究已經(jīng)進(jìn)行了一段時(shí)間，對(duì)TMS320C6678芯片針對(duì)雷達(dá)信號(hào)處理的并行開(kāi)發(fā)顯得尤為重要。本文主要內(nèi)容包括： 1.研究了TMS320C6678的Keystone多核架構(gòu)和內(nèi)核結(jié)構(gòu)以及實(shí)驗(yàn)室開(kāi)發(fā)的基于C6678的4DSP通用處理平臺(tái)，主要研究了C6678芯片中雷達(dá)信號(hào)處理實(shí)現(xiàn)中常用的SRIO接口、Hyperlink接口和EDMA3數(shù)據(jù)交互技術(shù)、常用的同步技術(shù)基于C6678的實(shí)現(xiàn)方案。 2.針對(duì)SAR成像的主要運(yùn)算FFT，研究了可進(jìn)行并行任務(wù)劃分的基于二維矩陣的FFT算法，在C6678片上小內(nèi)存的限制下，設(shè)計(jì)并行時(shí)序，利用多核聯(lián)合處理實(shí)現(xiàn)了超長(zhǎng)點(diǎn)數(shù)FFT運(yùn)算，包括基于C6678共享空間的單片并行處理和基于Hyperlink接口的多片并行處理，單片多核并行處理相較于單核處理效率基本實(shí)現(xiàn)線性提升，，多片聯(lián)合處理實(shí)現(xiàn)了小內(nèi)存空間限制下的更大點(diǎn)數(shù)FFT。 3.針對(duì)二維拆分FFT算法中的多核并行處理過(guò)程進(jìn)行優(yōu)化，包括了基于共享內(nèi)存的多核同步優(yōu)化，相較于常規(guī)的同步技術(shù)，速度提升5倍以上�；阢q鏈因子的內(nèi)存優(yōu)化，只存儲(chǔ)一行鉸鏈因子，通過(guò)其規(guī)律輔助計(jì)算其他鉸鏈因子，減小占用內(nèi)存空間百倍以上�；陔p緩沖區(qū)的并行優(yōu)化，將數(shù)據(jù)IO與內(nèi)核計(jì)算并行，進(jìn)一步縮短FFT計(jì)算時(shí)延。 4.設(shè)計(jì)了SAR雷達(dá)CS算法基于通用處理平臺(tái)的實(shí)現(xiàn)方案，應(yīng)用二維FFT多核并行處理算法，多核數(shù)據(jù)存儲(chǔ)技術(shù)和三角函數(shù)查表技術(shù)等，對(duì)CS算法的實(shí)現(xiàn)針對(duì)常規(guī)回波矩陣和大回波矩陣進(jìn)行了并行設(shè)計(jì)。
[Abstract]:With the continuous development of radar imaging technology, the requirements of imaging range, imaging accuracy and real-time processing are becoming higher and higher. In general, the use of single core DSP to complete computing has not been able to meet the change of requirements in this respect, and the parallel processing of multi-core DSP has become a trend of development. The research on TMS320C6678 multi-core DSP chips has been carried out for some time in the industry. The parallel development of TMS320C6678 chip for radar signal processing is particularly important. The main contents of this paper are as follows:. 1. The Keystone multi-core architecture and kernel structure of TMS320C6678 and the 4DSP general processing platform based on C6678 developed by the laboratory are studied. The SRIO interface and EDMA3 data interaction technology which is commonly used in radar signal processing in C6678 chip is mainly studied. The commonly used synchronization technology is based on the implementation of C 6678. 2. Aiming at the main operation of SAR imaging, the FFT algorithm based on 2-D matrix, which can be divided into parallel tasks, is studied. Under the limitation of small memory on C6678 chip, the parallel timing is designed, and the super-long FFT operation is realized by using multi-core joint processing. It includes single chip parallel processing based on C6678 shared space and multi chip parallel processing based on Hyperlink interface. Compared with single core processing, the efficiency of single chip multi core parallel processing is improved linearly. Multi-chip joint processing implements a larger number of FFTs under the limitation of small memory space. 3. The multi-core parallel processing process in the two-dimensional split FFT algorithm is optimized, including the multi-core synchronization optimization based on shared memory. Compared with the conventional synchronization technology, the speed is more than five times faster. Only a single line of hinge factors is stored, and the other hinge factors are calculated by its rule, which reduces the memory space by more than 100 times. Based on the parallel optimization of double buffers, the data IO is paralleled with the kernel computation to further shorten the computing delay of FFT. 4. The realization scheme of SAR radar CS algorithm based on general processing platform is designed. Two dimensional FFT multi-core parallel processing algorithm, multi-core data storage technology and trigonometric function look-up table technology are applied. The implementation of CS algorithm is designed in parallel for conventional echo matrix and large echo matrix.
【學(xué)位授予單位】：北京理工大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：TN957.52

【參考文獻(xiàn)】

相關(guān)期刊論文 前10條

1 吳一戎,胡東輝,彭海良;Chirp Scaling SAR成象算法及其實(shí)現(xiàn)[J];電子科學(xué)學(xué)刊;1995年03期

2 李鑫;姜明;;多核DSP高速實(shí)時(shí)信號(hào)處理系統(tǒng)設(shè)計(jì)[J];光學(xué)技術(shù);2012年01期

3 齊恩勇;;基于多核處理器的彈載嵌入式系統(tǒng)設(shè)計(jì)研究[J];電子設(shè)計(jì)工程;2013年06期

4 王順緒;;多核計(jì)算機(jī)上并行計(jì)算的實(shí)現(xiàn)與分析[J];淮海工學(xué)院學(xué)報(bào)(自然科學(xué)版);2009年03期

5 喬香珍;劉方愛(ài);;并行計(jì)算模型[J];計(jì)算機(jī)科學(xué);2002年07期

6 邢向磊;周余;都思丹;;基于ARM11 MPCore的多核間通信機(jī)制研究[J];計(jì)算機(jī)應(yīng)用與軟件;2009年05期

7 汪前進(jìn);高勇;李存華;;基于多核處理器的多任務(wù)并行處理技術(shù)研究[J];計(jì)算機(jī)應(yīng)用與軟件;2012年07期

8 杜金榜;鐘小鵬;王躍科;;多DSP并行處理系統(tǒng)的設(shè)計(jì)與開(kāi)發(fā)[J];計(jì)算機(jī)測(cè)量與控制;2006年05期

9 李錫武;毛先俊;;基于DSP的并行軟件系統(tǒng)的設(shè)計(jì)與實(shí)現(xiàn)[J];計(jì)算機(jī)工程與設(shè)計(jì);2007年21期

10 曹折波;李青;;多核處理器并行編程模型的研究與設(shè)計(jì)[J];計(jì)算機(jī)工程與設(shè)計(jì);2010年13期

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