發(fā)布時(shí)間：2018-02-15 23:22

  本文關(guān)鍵詞： 萬(wàn)兆FCoE 監(jiān)控 FPGA　出處：《電子科技大學(xué)》2014年碩士論文　論文類(lèi)型：學(xué)位論文

【摘要】：隨著科學(xué)技術(shù)的飛速發(fā)展,信息、數(shù)據(jù)處理和互聯(lián)網(wǎng)等技術(shù)也逐漸融入到人們的日常工作和生活當(dāng)中。對(duì)數(shù)據(jù)信息處理速度要求的不斷提高促使了數(shù)據(jù)中心的高速發(fā)展。數(shù)據(jù)中心中常見(jiàn)的網(wǎng)絡(luò)有最初的區(qū)域網(wǎng)絡(luò)(LAN)、存儲(chǔ)網(wǎng)絡(luò)(SAN)等,但前面兩者之間都有不足之處,此時(shí)就產(chǎn)生了融合兩者的FCo E技術(shù)。針對(duì)FCoE技術(shù)出現(xiàn)了融合網(wǎng)絡(luò)適配器(CNA)以及能處理FCoE的交換機(jī)、磁盤(pán)陣列、分析儀等。隨著這些設(shè)備的廣泛應(yīng)用,基于FCoE的網(wǎng)絡(luò)和設(shè)備之間的信息交互變得越來(lái)越復(fù)雜,同時(shí)對(duì)這些網(wǎng)絡(luò)和設(shè)備性能的要求也越來(lái)越高,而且這些設(shè)備的數(shù)據(jù)通信都不是透明的,為了能及時(shí)了解設(shè)備的通信情況,避免產(chǎn)生不必要的時(shí)間和經(jīng)濟(jì)損失,此時(shí)就需要能夠?qū)︖@些設(shè)備進(jìn)行實(shí)時(shí)監(jiān)控。而針對(duì)FCoE網(wǎng)絡(luò)的監(jiān)控測(cè)試設(shè)備的研究就有一定的經(jīng)濟(jì)意義。本文研究的是基于萬(wàn)兆FCoE的監(jiān)控卡,用于捕獲和分析萬(wàn)兆FCoE網(wǎng)絡(luò)上的數(shù)據(jù)。本文的硬件部分主要是實(shí)時(shí)將從10G以太網(wǎng)鏈路上捕獲的數(shù)據(jù)通過(guò)PCI Epress 2.0總線寫(xiě)入主機(jī)內(nèi)存,用于在主機(jī)界面上顯示抓獲的數(shù)據(jù)情況如數(shù)據(jù)類(lèi)型、數(shù)據(jù)總量、接收數(shù)據(jù)速率等,以便于對(duì)此時(shí)設(shè)備的通信情況能夠?qū)崟r(shí)的了解。同時(shí)用戶能夠通過(guò)設(shè)置觸發(fā)條件和過(guò)濾規(guī)則控制底層硬件對(duì)接收到的幀進(jìn)行觸發(fā)和過(guò)濾,這樣用戶可以提取所需要的幀而丟棄那些不需要的幀數(shù)據(jù),能夠節(jié)省時(shí)間提高工作效率。本文監(jiān)控卡的實(shí)現(xiàn)是基于FPGA的,采用Xilinx公司的Kintex-7XC7K325T開(kāi)發(fā)板。本文先簡(jiǎn)單介紹了光纖通道協(xié)議、萬(wàn)兆以太網(wǎng)、FCoE協(xié)議、DMA技術(shù)和PCI Express總線技術(shù),通過(guò)分析監(jiān)控卡的功能需求提出了監(jiān)控卡的總體設(shè)計(jì)方案;對(duì)設(shè)計(jì)中的兩大部分FCoE接口和DMA控制器分別進(jìn)行了詳細(xì)介紹,并對(duì)這兩個(gè)模塊通過(guò)Modelsim仿真工具進(jìn)行了功能仿真;在功能仿真符合設(shè)計(jì)要求后,和軟件進(jìn)行聯(lián)合測(cè)試,通過(guò)ISE工具將硬件代碼下載到開(kāi)發(fā)板上和CNA卡或者是磁盤(pán)陣列、FCoE交換機(jī)相連,進(jìn)行了詳細(xì)的分析和測(cè)試,通過(guò)Chipscope測(cè)試工具以及用戶界面得到的測(cè)試結(jié)果滿足了監(jiān)控卡的設(shè)計(jì)要求。
[Abstract]:With the rapid development of science and technology, information, Technologies such as data processing and the internet are gradually integrated into people's daily work and life. The increasing demand for the speed of data processing has promoted the rapid development of data centers. The common networks in data centers include:---. The original area network (LAN), the storage network (San), etc. However, there are some shortcomings between the two, and the FCoE technology that combines the two is produced. For the FCoE technology, there are converged network adapters and switches, disk arrays, which can handle FCoE. With the wide application of these devices, the information exchange between networks and devices based on FCoE becomes more and more complex, and the performance of these networks and devices is also becoming more and more demanding. Moreover, the data communication of these devices is not transparent. In order to understand the communication situation of the equipment in a timely manner and avoid unnecessary time and economic losses, At this time, we need to be able to monitor these devices in real time. And the research of monitoring and testing equipment for FCoE network has certain economic significance. The main hardware of this paper is to write the data captured from 10G Ethernet link to host memory through PCI Epress 2.0 bus in real time. Used to display captured data on the host interface such as data type, total amount of data, rate of receiving data, etc. At the same time, the user can control the bottom hardware to trigger and filter the received frame by setting the trigger condition and filtering rules. In this way, the user can extract the needed frames and discard the unnecessary frame data, which can save time and improve the efficiency. The implementation of this monitoring card is based on FPGA. This paper introduces the optical fiber channel protocol, Gigabit Ethernet FCoE protocol and PCI Express bus technology, and puts forward the overall design scheme of the monitoring card by analyzing the functional requirements of the monitoring card. The two parts of FCoE interface and DMA controller in the design are introduced in detail, and the two modules are simulated by Modelsim simulation tools, after the functional simulation meets the design requirements, the two modules are tested jointly with the software. The hardware code is downloaded to the development board by the ISE tool and connected to the CNA card or the disk array FCoE switch. It is analyzed and tested in detail. The test results obtained through the Chipscope test tool and the user interface meet the design requirements of the monitoring card.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類(lèi)號(hào)】：TN929.11

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本文編號(hào)：1514123