本文關(guān)鍵詞： 高清分辨率 CABAC HLS 流水　出處：《西安電子科技大學(xué)》2014年碩士論文　論文類型：學(xué)位論文

【摘要】：隨著信息化時(shí)代的到來,越來越多的高清分辨率甚至超清分辨率的視頻出現(xiàn)在人們的生活中,實(shí)時(shí)對這類視頻進(jìn)行壓縮并傳輸?shù)男枨笠苍絹碓蕉唷?013年1月JCT-VC發(fā)布了最新的視頻壓縮標(biāo)準(zhǔn)HEVC。該標(biāo)準(zhǔn)采用了基于四叉樹的編碼組織結(jié)構(gòu)以及更大尺寸的編碼塊,加入了更多的預(yù)測方向,其壓縮效率比現(xiàn)有的H.264標(biāo)準(zhǔn)高了一倍。HEVC標(biāo)準(zhǔn)采用基于上下文模型的二進(jìn)制算術(shù)編碼(Context-based Adaptive Binary Arithmetic Coding,CABAC)作為其熵編碼的編碼算法。CABAC在HEVC中的作用非常重要,它根據(jù)精確的上下文概率模型對殘差信息進(jìn)行編碼,達(dá)到了接近香農(nóng)熵的編碼性能。但是由于CABAC的工作模式為串行逐比特編碼,使得它成為了HEVC視頻壓縮的主要瓶頸。賽靈思公司近年來新推出的高級綜合工具(High-Level-Synthesis,HLS),它幫助工程師隱藏了寄存器轉(zhuǎn)換級(Register Transfer Lever,RTL)設(shè)計(jì)和現(xiàn)場可編程邏輯器件(Field-Programmable Gate Array,FPGA)結(jié)構(gòu)的細(xì)節(jié),其驗(yàn)證過程也較為簡單,能夠大幅地減少硬件系統(tǒng)的開發(fā)周期。為了解決CABAC吞吐率瓶頸的問題,本文在仔細(xì)研究了HEVC標(biāo)準(zhǔn)和CABAC算法原理的基礎(chǔ)上,從算法上分析CABAC的速度瓶頸,并且使用HLS工具進(jìn)行CABAC的硬件設(shè)計(jì)實(shí)現(xiàn)。本文的主要工作有:1.提出了一種多級流水的CABAC實(shí)現(xiàn)架構(gòu)。將CABAC劃分成比特編碼、碼流打包和碼流輸出三個(gè)子模塊,通過分支預(yù)測技術(shù)去除了比特編碼模塊和碼流輸出模塊之間的數(shù)據(jù)相關(guān)性,在三個(gè)模塊間建立起多級流水線,提高了CABAC的數(shù)據(jù)吞吐率。2.利用HLS工具完成了滿足4K實(shí)時(shí)視頻編碼的CABAC實(shí)現(xiàn)。針對提出的CABAC的硬件架構(gòu),利用HLS工具分別對CABAC的常規(guī)編碼模式和旁路編碼模式進(jìn)行實(shí)現(xiàn)和相應(yīng)優(yōu)化;通過partition約束將數(shù)組映射為寄存器以提高數(shù)據(jù)訪問速度,通過unroll約束將串行執(zhí)行的循環(huán)體映射為并行執(zhí)行的循環(huán)體以縮短處理時(shí)延;通過pipeline約束在多個(gè)模塊間建立流水線以最終實(shí)現(xiàn)一種多級流水的可實(shí)時(shí)編碼的CABAC的硬件架構(gòu);最后將所設(shè)計(jì)的CABAC編碼器架構(gòu)利用HLS工具進(jìn)行RTL功能仿真。本文針對HEVC中CABAC的硬件實(shí)現(xiàn),提出了一種多級流水的硬件架構(gòu),并通過HLS工具實(shí)現(xiàn)。實(shí)驗(yàn)結(jié)果表明,該架構(gòu)能夠獲得比較高的數(shù)據(jù)吞吐率,滿足4K分辨率視頻實(shí)時(shí)壓縮的需求。本文所提出的CABAC編碼器的核心架構(gòu),其算法復(fù)雜度低,可通過單片F(xiàn)PGA實(shí)現(xiàn),具有很高的實(shí)際應(yīng)用價(jià)值。
[Abstract]:With the advent of the information age, more and more high-definition and even super-resolution video appear in people's lives. In January 2013, JCT-VC released the latest video compression standard, HEVC, which uses a quadtree based coding organization and larger coding blocks. By adding more prediction directions, its compression efficiency is twice as high as the existing H.264 standard. The Contex-based Adaptive Binary Arithmetic coding algorithm, named Contex-based Adaptive Binary Arithmetic coding algorithm, is used as the coding algorithm in HEVC. It is very important for the HEVC standard to use the Context-based Adaptive Binary Arithmetic coding method as its coding algorithm. It encodes the residual information according to the accurate context probability model, which achieves the coding performance close to Shannon entropy. However, because the CABAC work mode is serial bit by bit coding, It has become a major bottleneck in HEVC video compression. The company's new advanced integration tool, High-Level-Synsissis, has helped engineers hide the details of the register-conversion level Register Transfer ever#en0# design and the Field-Programmable Gate ArrayFPGA architecture. In order to solve the bottleneck problem of CABAC throughput, this paper analyzes the speed bottleneck of CABAC on the basis of studying the HEVC standard and the principle of CABAC algorithm. The main work of this paper is: 1. A multilevel income CABAC implementation architecture is proposed. The CABAC is divided into three sub-modules: bit coding, bitstream packaging and stream output. The data correlation between the bit-coding module and the bit-stream output module is removed by the branch prediction technology, and a multi-level pipeline is established among the three modules. The data throughput of CABAC is improved. 2. The implementation of CABAC for 4K real-time video coding is accomplished by using HLS tools. The hardware architecture of CABAC is proposed. The conventional encoding mode and bypass coding mode of CABAC are realized and optimized by using HLS tool, and the array is mapped to register by partition constraint to improve the data access speed. The serial execution loop body is mapped to the parallel execution loop body by unroll constraint to shorten the processing delay, pipeline is set up among several modules by pipeline constraint to realize a multistage income real-time encoding CABAC hardware architecture. Finally, the designed CABAC encoder architecture is simulated with HLS tools for RTL function. Aiming at the hardware implementation of CABAC in HEVC, a kind of multilevel income hardware architecture is proposed and implemented by HLS tool. The experimental results show that, This architecture can achieve high data throughput and meet the demand of real-time video compression with 4K resolution. The core architecture of CABAC encoder presented in this paper has low algorithm complexity and can be realized by single chip FPGA. It has high practical application value.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TN919.81

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