本文關(guān)鍵詞： V-by-One 發(fā)送器 4K傳輸　出處：《西安電子科技大學(xué)》2014年碩士論文　論文類型：學(xué)位論文

【摘要】：V-by-One是一種新近興起串口通信標(biāo)準(zhǔn),該標(biāo)準(zhǔn)開發(fā)的主要目的是為了替代VESA標(biāo)準(zhǔn)的LVDS技術(shù),其主要優(yōu)勢(shì)包括:能夠滿足最高4Gbps的帶寬傳輸(有效傳輸率3.2Gbps);不帶時(shí)鐘傳輸;可以傳輸3D格式視頻和網(wǎng)絡(luò)電視;支持4K分辨率,縱橫比為21:9等。隨著4K智能電視時(shí)代的來臨,V-by-One技術(shù)憑借其特有優(yōu)勢(shì)必將取得更加廣泛推廣和應(yīng)用,因此在電視中如何用V-by-One技術(shù)實(shí)現(xiàn)視頻傳輸將會(huì)是一個(gè)新的研究熱點(diǎn)。在以上背景下,本文基于4K 60Hz視頻傳輸?shù)脑O(shè)計(jì)目標(biāo),在充分研究V-by-One協(xié)議基礎(chǔ)上,提出一種支持4K 60Hz視頻傳輸?shù)腣-by-One數(shù)字發(fā)送器電路的8通道傳輸方案。該方案基于模塊復(fù)用思想,將發(fā)送器分為對(duì)稱的兩個(gè)塊,設(shè)計(jì)時(shí)只需考慮實(shí)現(xiàn)一個(gè)塊的4通道傳輸。與一般8通道傳輸方案相比,本文方案降低了發(fā)送器的控制難度和時(shí)鐘需求,且后續(xù)可以很方便的進(jìn)行通道拓展來支持更高幀率的4K視頻傳輸。本文研究并實(shí)現(xiàn)了以下規(guī)格的V-by-One數(shù)字發(fā)送器電路設(shè)計(jì):支持YCbCr444/422、RGB等顏色格式;支持6/8/10/12bit等色彩深度;支持1/2/4/8的可配置傳輸通道數(shù);輸出鏈路順序可控;最高工作頻率400 MHz;滿足V-by-One1.4協(xié)議。本文設(shè)計(jì)8B10B編碼器時(shí),在分析傳統(tǒng)查找表電路實(shí)現(xiàn)方案基礎(chǔ)上,基于協(xié)議規(guī)定的編碼需求,研究并提出一種新的編碼電路實(shí)現(xiàn)方案。相比傳統(tǒng)方案,本文方案使用邏輯運(yùn)算結(jié)合查找表方式來編碼,所需碼表存儲(chǔ)大小從272 bit減小為44bit,降低了83.8%。本文方案對(duì)D碼和K碼統(tǒng)一處理,簡(jiǎn)化了RD控制結(jié)構(gòu)。本文對(duì)實(shí)現(xiàn)的發(fā)送器電路,根據(jù)設(shè)計(jì)規(guī)格作了充分的測(cè)試點(diǎn)分解并搭建驗(yàn)證平臺(tái)進(jìn)行了功能驗(yàn)證。具體功能驗(yàn)證時(shí),本文針對(duì)各個(gè)功能模塊和發(fā)送器整體的仿真結(jié)果作了詳細(xì)分析,同時(shí)統(tǒng)計(jì)驗(yàn)證代碼覆蓋率為98.3%,保證了驗(yàn)證工作的正確性和完備性。本文選用Cyclone III系列的EP3C16F484C6器件,在Quartus II13.0平臺(tái)上對(duì)發(fā)送器進(jìn)行了FPGA綜合和時(shí)序分析,其結(jié)果表明發(fā)送器電路在400 MHz最大目標(biāo)工作頻率下時(shí)序可收斂,從而證明本文設(shè)計(jì)發(fā)送器可以滿足4K 60Hz視頻傳輸目標(biāo)。
[Abstract]:V-by-One is a newly rising serial communication standard. The main purpose of this standard is to replace the LVDS technology of VESA standard. Its main advantages include: being able to meet up to 4Gbps bandwidth transmission (effective transmission rate 3.2Gbps); No clock transmission; Can transmit 3D format video and network TV; Support 4K resolution, aspect ratio is 21: 9. With the advent of 4K intelligent television era, V-by-One technology will be more widely spread and applied with its unique advantages. Therefore, how to realize video transmission with V-by-One technology in TV will be a new research hotspot. Under the above background, this paper based on the design goal of 4K60Hz video transmission. Based on the research of V-by-One protocol. An 8-channel transmission scheme for V-by-one digital transmitter circuit supporting 4K60Hz video transmission is proposed. Based on the idea of module reuse, the transmitter is divided into two symmetrical blocks. The design only need to consider the implementation of a block of 4-channel transmission. Compared with the general 8-channel transmission scheme, this scheme reduces the control difficulty and clock requirements of the transmitter. And the subsequent channel can be easily extended to support higher frame rate 4K video transmission. This paper studies and implements the following specifications of the V-by-One digital transmitter circuit design:. Support for YCbCr444/422. Color format such as RGB; Support 6 / 8 / 10 / 12 bit color depth; The number of configurable transmission channels that support 1 / 2 / 4 / 8; Output link sequence is controllable; The highest working frequency is 400 MHz; This paper designs 8B10B encoder, on the basis of analyzing the realization scheme of traditional look-up table circuit, based on the coding requirement stipulated by the protocol. This paper studies and proposes a new scheme of coding circuit. Compared with the traditional scheme, this scheme uses logic operation combined with look-up table to code. The storage size of the code table is reduced from 272 bit to 44 bits, which is 83.8. the scheme of this paper unifies the processing of D code and K code. The structure of Rd control is simplified. According to the design specification, the circuit of transmitter is decomposed according to the design specification, and the verification platform is built for functional verification. In this paper, the simulation results of each function module and transmitter are analyzed in detail, and the code coverage of statistical verification is 98.3%. The correctness and completeness of the verification work are ensured. In this paper, the EP3C16F484C6 devices of Cyclone III series are selected. The FPGA synthesis and timing analysis of the transmitter are carried out on the Quartus II13.0 platform. The results show that the transmitter circuit can converge at the maximum target frequency of 400 MHz. It is proved that the transmitter designed in this paper can meet the target of 4K 60 Hz video transmission.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：TN919.81

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