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  本文關(guān)鍵詞： m序列 RS碼 交織碼 卷積碼 Viterbi譯碼 CPFSK FPGA　出處：《南京理工大學(xué)》2014年碩士論文　論文類型：學(xué)位論文

【摘要】：本文主要設(shè)計實現(xiàn)了CPFSK調(diào)制解調(diào)通信系統(tǒng),系統(tǒng)中包含m序列加密解密電路、RS編譯碼電路、交織與解交織電路、卷積編譯碼電路以及CPFSK調(diào)制解調(diào)電路。 文中首先設(shè)計了系統(tǒng)的總體框圖,然后對系統(tǒng)中的各個電路的設(shè)計與實現(xiàn)作了深入的研究。在系統(tǒng)的加密部分中,本文基于m序列設(shè)計32級m序列加密解密電路,并在FPGA的硬件基礎(chǔ)上,采用Verilog語言實現(xiàn)了32級m序列加密解密電路；在系統(tǒng)的糾錯碼中,采用了RS(255,239)碼與(2,1,7)卷積碼級聯(lián)的方式,并在兩編碼器的級聯(lián)中間插入了交織器,以提高糾錯系統(tǒng)的糾錯性能；對于RS(255,239)碼的編碼電路,本文對其傳統(tǒng)的編碼算法進(jìn)行了改進(jìn),并在FPGA的硬件基礎(chǔ)上,采用Verilog語言實現(xiàn)了RS(255,239)編碼電路,并基于Altera的IP核實現(xiàn)了RS(255,239)碼的譯碼電路；在研究RS編譯碼電路中,還研究了電路工作過程中遇到的碼率匹配問題和串并轉(zhuǎn)換問題,并提出了該問題的解決方案,在FPGA的硬件基礎(chǔ)上,采用Verilog語言設(shè)計實現(xiàn)了碼率匹配電路和串并轉(zhuǎn)換電路；交織器本文采用卷積交織的方法來實現(xiàn),并在FPGA的硬件基礎(chǔ)上,采用Verilog語言實現(xiàn)了交織與解交織電路；對于(2,1,7)卷積碼的編碼電路,本文在FPGA的硬件基礎(chǔ)上,采用Verilog語言實現(xiàn)了(2,1,7)卷積編碼電路,而(2,1,7)卷積碼的譯碼電路,本文采用Viterbi譯碼算法來實現(xiàn),并基于Altera的IP核實現(xiàn)了Viterbi譯碼電路；最后,CPFSK調(diào)制解調(diào)電路采用了其特殊的一種方式MSK調(diào)制,采用Verilog語言設(shè)計實現(xiàn)了MSK經(jīng)典的正交調(diào)制電路,并在DFT算法的基礎(chǔ)上,設(shè)計了一種更加簡單有效的MSK解調(diào)方案,采用Verilog語言實現(xiàn)了該解調(diào)電路。在硬件實現(xiàn)的同時,本文還在Matlab平臺上對各個模塊進(jìn)行了仿真驗證,確保電路設(shè)計的正確性。
[Abstract]:This paper mainly designs and implements the communication system of CPFSK modulation and demodulation, which includes m sequence encryption and decryption circuit, RS encoding and decoding circuit, interleaving circuit and deinterleaving circuit. Convolution encoding and decoding circuit and CPFSK modulation and demodulation circuit. In this paper, the overall block diagram of the system is first designed, and then the design and implementation of each circuit in the system are deeply studied. In the encryption part of the system. In this paper, a 32-level m sequence encryption and decryption circuit is designed based on m sequence. Based on the hardware of FPGA, the 32-level m sequence encryption and decryption circuit is implemented by Verilog language. In the error correction code of the system, the scheme of concatenation of RSH255N239) code and the convolutional code of 2H2P1H7) is adopted, and an interleaver is inserted between the concatenations of the two encoders. To improve the error-correcting performance of the system; In this paper, the traditional coding algorithm is improved and based on the hardware of FPGA, the encoding circuit of RSH255N239) code is improved. The RSF255P239) coding circuit is realized by using Verilog language, and the decoding circuit of RSH255P239) code is realized based on the IP core of Altera. In the research of RS codec circuit, the rate matching problem and the serial-parallel conversion problem encountered in the working process of the circuit are also studied, and the solution to this problem is put forward, based on the hardware of FPGA. The bit-rate matching circuit and the series-parallel conversion circuit are designed and implemented by using Verilog language. The Interleaver is implemented by convolution interleaving method, and based on the hardware of FPGA, the interleaving and deinterleaving circuits are implemented by Verilog language. On the basis of the hardware of FPGA, this paper uses Verilog language to realize the coding circuit of the convolutional code. 7) the decoding circuit of convolutional code is realized by Viterbi decoding algorithm, and the Viterbi decoding circuit is implemented based on IP core of Altera. Finally, the CPFSK modulation and demodulation circuit adopts its special way of MSK modulation, and the MSK classic quadrature modulation circuit is designed and implemented by Verilog language. On the basis of DFT algorithm, a more simple and effective MSK demodulation scheme is designed. The demodulation circuit is realized by Verilog language. In order to ensure the correctness of the circuit design, the simulation of each module is carried out on the Matlab platform.
【學(xué)位授予單位】：南京理工大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TN915.05

【參考文獻(xiàn)】

相關(guān)期刊論文 前10條

1 楊永輝;李朔;李景杰;;基于m序列和擾亂技術(shù)的數(shù)據(jù)通信的加密和解密[J];鞍山科技大學(xué)學(xué)報;2006年05期

2 徐元欣,王匡,仇佩亮;實現(xiàn)卷積交織的幾種實用方法[J];電路與系統(tǒng)學(xué)報;2001年01期

3 馬金嶺;劉桂敏;梁凱;;基于IP核的Viterbi譯碼器實現(xiàn)[J];信息化研究;2010年02期

4 王玲;一種交織器和解交織器的FPGA電路實現(xiàn)[J];今日電子;2001年12期

5 顧烊;張萌;孫偉;楊東;;一種面向RS碼的卷積交織與解交織器的設(shè)計[J];電子器件;2006年02期

6 嚴(yán)立中;張正華;;相位連續(xù)頻移鍵控相干解調(diào)載波的提取[J];國外電子測量技術(shù);2005年12期

7 甘露;劉宗輝;廖紅舒;李立萍;;卷積交織參數(shù)的盲估計[J];電子學(xué)報;2011年09期

8 范寒柏,宋文妙;數(shù)據(jù)通信中交織與解交織的FPGA實現(xiàn)[J];華北電力大學(xué)學(xué)報;2002年02期

9 趙輝;趙旦峰;侯長波;朱鐵林;;MSK調(diào)制解調(diào)器的設(shè)計與實現(xiàn)[J];哈爾濱理工大學(xué)學(xué)報;2011年01期

10 彭國祥;典型船用MSK調(diào)制解調(diào)器的組成和工作原理分析[J];世界海運;2004年05期

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本文編號：1467567