本文關(guān)鍵詞： 準(zhǔn)循環(huán)LDPC碼 編碼器 分層譯碼器 高斯白噪聲 TDMP FPGA　出處：《北京郵電大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

【摘要】：自從上世紀(jì)90年代開始,LDPC碼重新引起了人們的重視。由于其性能接近香農(nóng)極限,LDPC碼已經(jīng)廣泛應(yīng)用于DVB-S2、CMMB、4G通信系統(tǒng)、衛(wèi)星通信和數(shù)字水印系統(tǒng)。目前,在航天領(lǐng)域的多個(gè)預(yù)研項(xiàng)目中,都在論證采用LDPC碼提高系統(tǒng)性能的可行性。 LDPC碼的優(yōu)化設(shè)計(jì)是一項(xiàng)復(fù)雜的工作,每優(yōu)化出一個(gè)碼都需要對其性能進(jìn)行仿真評估。很多應(yīng)用場景對LDPC的錯(cuò)誤平層有較高要求,仿真需要達(dá)到10-7以下的誤比特率,因此仿真的數(shù)據(jù)量至少要達(dá)到109比特,對如此大量的數(shù)據(jù)進(jìn)行軟件仿真必然需要耗費(fèi)大量的計(jì)算時(shí)間。本文試圖基于FPGA設(shè)計(jì)一款針對準(zhǔn)循環(huán)LDPC碼的硬件仿真器,能夠在很短的時(shí)間內(nèi)實(shí)現(xiàn)對于某種LDPC碼性能的仿真評估。 圍繞LDPC碼硬件仿真器設(shè)計(jì)這一目標(biāo),本文主要完成了以下工作。首先,研究了基于準(zhǔn)循環(huán)生成矩陣的QC-LDPC碼的編碼算法和其SRAA電路實(shí)現(xiàn)原理,重點(diǎn)研究了基于準(zhǔn)循環(huán)校驗(yàn)矩陣的編碼算法,通過利用其雙對角線化結(jié)構(gòu)特征推導(dǎo)出校驗(yàn)比特的迭代計(jì)算公式,在FPGA平臺上實(shí)現(xiàn)了高吞吐率編碼。其次,研究和比較了多種不同的譯碼算法的性能、迭代收斂速度及其實(shí)現(xiàn)方法,重點(diǎn)研究了結(jié)構(gòu)化的QC-LDPC碼的分層譯碼算法,并在FPGA平臺上實(shí)現(xiàn)了基于這種算法的通用譯碼器。最后,設(shè)計(jì)了外圍的隨機(jī)數(shù)據(jù)源模塊、映射模塊、軟解調(diào)模塊、高斯白噪聲發(fā)生器模塊和誤碼率統(tǒng)計(jì)模塊,與準(zhǔn)循環(huán)LDPC編碼器和譯碼器一起構(gòu)成了準(zhǔn)循環(huán)LDPC碼硬件仿真器,可以通過配置不同校驗(yàn)矩陣參數(shù)和噪聲方差,實(shí)現(xiàn)大量數(shù)據(jù)的快速仿真。
[Abstract]:Since -10s, LDPC codes have attracted more and more attention. Since their performance is close to the Shannon limit, LDPC codes have been widely used in DVB-S2CMB. 4G communication system, satellite communication and digital watermarking system. At present, the feasibility of using LDPC code to improve system performance is demonstrated in many pre-research projects in aerospace field. The optimal design of LDPC codes is a complex task, each optimization of a code needs to be evaluated by simulation. Many application scenarios have higher requirements for the error level of LDPC. Simulation needs to achieve a bit error rate below 10-7, so the amount of data must be at least 109 bits. Software simulation of such a large amount of data is bound to cost a lot of computing time. This paper attempts to design a hardware simulator for quasi-cyclic LDPC code based on FPGA. The performance of a certain LDPC code can be evaluated in a very short time. Focusing on the design of LDPC code hardware simulator, this paper mainly completes the following work. First of all. The coding algorithm of QC-LDPC code based on quasi-cyclic generation matrix and its realization principle of SRAA circuit are studied, and the coding algorithm based on quasi-cyclic check matrix is studied emphatically. By using its dual diagonal linearized structure feature, the iterative calculation formula of the check bit is deduced, and the high throughput coding is realized on the FPGA platform. Secondly, the performance of different decoding algorithms is studied and compared. The iterative convergence rate and its implementation method are discussed. The hierarchical decoding algorithm of structured QC-LDPC codes is studied, and a general decoder based on this algorithm is implemented on the FPGA platform. Finally. The peripheral random data source module, mapping module, soft demodulation module, Gao Si white noise generator module and error rate statistics module are designed. A hardware simulator for quasi-cyclic LDPC codes is constructed with quasi-cyclic LDPC encoders and decoders. The fast simulation of a large number of data can be realized by configuring different parameters of check matrix and noise variance.
【學(xué)位授予單位】：北京郵電大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN911.22

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本文編號：1466799