本文關(guān)鍵詞： LTE-A Turbo 并行編碼 并行譯碼 FPGA實(shí)現(xiàn)　出處：《電子科技大學(xué)》2014年碩士論文　論文類(lèi)型：學(xué)位論文

【摘要】：隨著人們對(duì)業(yè)務(wù)層面需求的增加和提高,對(duì)移動(dòng)通信系統(tǒng)的寬帶化要求也越來(lái)越高,因此,選擇一種具有良好譯碼性能的信道編碼以提高傳輸信息的可靠性就顯得非常重要。經(jīng)過(guò)長(zhǎng)期方案評(píng)估,3GPP選擇Turbo碼作為第四代移動(dòng)通信系統(tǒng)——LTE-A系統(tǒng)的編碼方案。2013年12月4日,國(guó)家工信部向三大運(yùn)營(yíng)商發(fā)放4G牌照,預(yù)示著對(duì)LTE-A系統(tǒng)中Turbo碼的研究將隨之備受關(guān)注。本文分析了適用于LTE-A系統(tǒng)的Turbo編碼算法和Turbo譯碼算法。對(duì)于編碼,可以直接根據(jù)LTE-A協(xié)議進(jìn)行設(shè)計(jì);對(duì)于Turbo譯碼,本文首先研究了適用于LTE-A系統(tǒng)的高階軟解調(diào)算法的基本原理,并分析和比較了四種不同譯碼算法(SOVA,MAP,LOG-MAP,MAX-LOG-MAP)的原理、性能和復(fù)雜性,在犧牲很小性能的前提下,選擇MAX-LOG-MAP算法作為硬件實(shí)現(xiàn)算法。另外,本文還著重分析了編碼算法和譯碼算法的并行化處理。傳統(tǒng)的編碼算法利用移位寄存器,任意時(shí)刻的寄存器狀態(tài)都跟之前的輸入比特有關(guān),無(wú)法實(shí)現(xiàn)并行化以提高吞吐量,所以本文設(shè)計(jì)了一種基于查找表的實(shí)現(xiàn)方法解決了這個(gè)問(wèn)題。同時(shí),本文分析了QPP交織器的無(wú)地址爭(zhēng)用,無(wú)訪問(wèn)沖突的特點(diǎn),在此基礎(chǔ)上,分析了譯碼算法的并行交織和并行解交織并仿真了不同并行度對(duì)MAX-LOG-MAP譯碼性能的影響,由于非常有效的子譯碼器的初始化策略,并行MAX-LOG-MAP譯碼算法相對(duì)于串行MAX-LOG-MAP譯碼算法并沒(méi)有太大的性能損失(對(duì)于幀長(zhǎng)為40比特的譯碼,8并行度的譯碼損失僅為0.7dB左右)。在算法分析的基礎(chǔ)上,本文設(shè)計(jì)了LTE-A系統(tǒng)中的Turbo編碼器和Turbo譯碼器的并行化結(jié)構(gòu)(8并行度)。并詳細(xì)分析了各個(gè)子模塊的接口、核心電路、仿真結(jié)果以及總體硬件資源消耗情況,最后在Altera DE4(芯片型號(hào):EP4S40G5H40I2)上對(duì)所設(shè)計(jì)的硬件電路進(jìn)行板級(jí)測(cè)試。本文所設(shè)計(jì)的Turbo編碼器的資源占有率不到1%(其中組合邏輯單元使用個(gè)數(shù)為477個(gè),占有率小于1%;寄存器使用個(gè)數(shù)為762個(gè),占有率小于1%),最高時(shí)鐘頻率可以達(dá)到315.06 MHz,最大吞吐量可以達(dá)到2.52 Gbit/s;Turbo譯碼器的資源占有率為15%(其中組合邏輯單元使用個(gè)數(shù)為47084個(gè),占有率為11%;存儲(chǔ)單元使用個(gè)數(shù)為4826個(gè),占有率為2%;寄存器使用個(gè)數(shù)為54251個(gè),占有率為13%),最高時(shí)鐘頻率可以達(dá)到175.87 MHz,最大吞吐量可以達(dá)到175.87Mbit/s。
[Abstract]:With the increase and improvement of people's demand for service level, the requirement of broadband for mobile communication system is becoming more and more high. It is very important to select a channel code with good decoding performance to improve the reliability of transmission information. 3GPP chooses Turbo code as the coding scheme of 4th generation mobile communication system-LTE-A system. In December 4th 2013, the Ministry of Industry and Information Technology issued 4G licenses to three major operators. It indicates that the study of Turbo code in LTE-A system will be paid more attention. This paper analyzes the Turbo coding algorithm and Turbo decoding algorithm suitable for LTE-A system. It can be designed directly according to LTE-A protocol. For Turbo decoding, the basic principle of high order soft demodulation algorithm for LTE-A system is studied, and four different decoding algorithms are analyzed and compared. The principle, performance and complexity of LOG-MAPG MAX-LOG-MAP.On the premise of sacrificing very small performance, MAX-LOG-MAP algorithm is chosen as the hardware implementation algorithm. This paper also analyzes the parallelization of coding algorithm and decoding algorithm. The traditional coding algorithm uses shift register, and the register state at any time is related to the previous input bit. It is impossible to achieve parallelization to improve throughput, so this paper designs an implementation method based on lookup table to solve this problem. At the same time, this paper analyzes the QPP Interleaver without address contention. On the basis of this, the parallel interleaving and parallel deinterleaving of decoding algorithm are analyzed and the influence of different parallelism degree on MAX-LOG-MAP decoding performance is simulated. Because of the very effective initialization strategy of the sub-decoder. The parallel MAX-LOG-MAP decoding algorithm has no significant performance loss compared with the serial MAX-LOG-MAP decoding algorithm. The decoding loss of parallelism is only about 0.7 dB. In this paper, the parallelization structure of Turbo encoder and Turbo decoder in LTE-A system is designed, and the interface and core circuit of each sub-module are analyzed in detail. Simulation results and overall hardware resource consumption. Finally in Altera DE4 (chip type: EP4S40G5H40I2). The Turbo encoder designed in this paper has less than 1 share of resources (the number of combinational logic units is 477. The occupation rate is less than 1%; The number of registers used is 762, the occupancy rate is less than 1 bit, the highest clock frequency can reach 315.06 MHz, and the maximum throughput can reach 2.52 Gbit / s; The resource share of Turbo decoder is 15. Among them, the number of combinational logic units is 47084, and the occupation rate is 11. The number of memory units is 4826, and the occupation rate is 2. The number of registers used is 54251, the occupancy rate is 13, the highest clock frequency can reach 175.87 MHz, and the maximum throughput can reach 175.87 Mbit / s.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類(lèi)號(hào)】：TN929.5;TN911.22

【參考文獻(xiàn)】

相關(guān)碩士學(xué)位論文 前1條

1 蘇棟;分塊歸零處理TURBO編譯碼器FPGA設(shè)計(jì)與實(shí)現(xiàn)[D];西南交通大學(xué);2010年

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本文編號(hào)：1455099