發(fā)布時間：2018-01-20 03:25

  本文關(guān)鍵詞： 高速接口 PCIe WinDriver 千兆以太網(wǎng)口 Winpcap　出處：《西安電子科技大學(xué)》2014年碩士論文　論文類型：學(xué)位論文

【摘要】：隨著系統(tǒng)性能、功能和帶寬的提高,高速數(shù)據(jù)采集與記錄以及其他數(shù)據(jù)處理的數(shù)據(jù)吞吐量都日益增長。因此通過研究發(fā)展新的高速接口技術(shù)來解決帶寬限制和高速傳輸這些關(guān)鍵問題是一種必然趨勢和迫切的需求。FPGA已發(fā)展成為實現(xiàn)數(shù)字系統(tǒng)的主流平臺之一,廣泛應(yīng)用于信號處理及通信等各個領(lǐng)域。FPGA在信號處理時可并行運行,處理速度快,但不適合實現(xiàn)高精度復(fù)雜的運算處理。而PC計算機具備相當強大的計算和數(shù)據(jù)處理能力,所以通常情況下會將需要進行高精度復(fù)雜的計算交由計算機負責(zé)處理。這就涉及到FPGA與PC間進行大量數(shù)據(jù)的傳輸問題,因此構(gòu)建PC機與FPGA的高速數(shù)據(jù)傳輸系統(tǒng)成為當前的研究趨勢。本文根據(jù)當前研究趨勢和實際科研項目要求,對PCIe和千兆以太網(wǎng)進行了深入研究,并設(shè)計了PCIe DMA數(shù)據(jù)傳輸系統(tǒng)和千兆以太網(wǎng)數(shù)據(jù)傳輸系統(tǒng)來實現(xiàn)FPGA與PC機之間的數(shù)據(jù)通信。本文的具體工作如下:1.深入研究PCIe和千兆以太網(wǎng),了解PCIe和千兆以太網(wǎng)的技術(shù)優(yōu)勢,具體分析PCIe和千兆以太網(wǎng)的傳輸協(xié)議,詳細說明PCIe TLP數(shù)據(jù)包格式和以太網(wǎng)標準數(shù)據(jù)幀格式。2.完成PCIe DMA數(shù)據(jù)傳輸系統(tǒng)設(shè)計。設(shè)計方案主要包括兩大部分,分別是FPGA端Verilog邏輯模塊開發(fā)以及PC端的驅(qū)動和C應(yīng)用程序開發(fā)。FPGA端基于PCIe IP Core完成了發(fā)送接收引擎模塊、寄存器讀寫控制模塊和FIFO讀寫控制模塊的設(shè)計。定義了相應(yīng)模塊的接口,并分析了數(shù)據(jù)傳輸?shù)臅r序。PC端采用WinDriver進行PCIe的驅(qū)動開發(fā),并根據(jù)WinDriver提供的驅(qū)動API函數(shù)完成C應(yīng)用程序的設(shè)計。3.完成千兆以太網(wǎng)數(shù)據(jù)傳輸系統(tǒng)設(shè)計。設(shè)計方案也主要包括兩大部分,分別是FPGA端Verilog邏輯模塊開發(fā)以及PC端Winpcap應(yīng)用程序開發(fā)。FPGA端基于嵌入式三態(tài)以太網(wǎng)MAC IP Core,設(shè)計了發(fā)送接收引擎模塊、FIFO讀寫控制模塊和物理接口模塊。定義了相應(yīng)模塊的接口,并分析了數(shù)據(jù)傳輸經(jīng)過LocalLink接口和Client用戶接口上的傳輸時序。PC端采用Winpcap提供的網(wǎng)絡(luò)編程完成了C應(yīng)用程序的設(shè)計,實現(xiàn)了捕獲FPGA端發(fā)送的數(shù)據(jù)包以及發(fā)送原始數(shù)據(jù)包至FPGA端的功能。4.PCIe DMA數(shù)據(jù)傳輸系統(tǒng)和千兆以太網(wǎng)數(shù)據(jù)傳輸系統(tǒng)在Xilinx ML507開發(fā)板上進行了性能測試。記錄FPGA與PC間進行讀寫測試的結(jié)果,驗證這兩個系統(tǒng)的可用性和穩(wěn)定性,最后分析了影響系統(tǒng)傳輸速率的原因以及系統(tǒng)目前仍存在的不足。本文設(shè)計的PCIe DMA數(shù)據(jù)傳輸系統(tǒng)和千兆以太網(wǎng)數(shù)據(jù)傳輸系統(tǒng)基本實現(xiàn)了FPGA與PC間大量數(shù)據(jù)的快速傳輸,對后續(xù)科研做出了一定的貢獻。
[Abstract]:With the improvement of system performance, function and bandwidth. The data throughput of high speed data acquisition and recording and other data processing is increasing, so it is an inevitable trend to solve the key problems of bandwidth limitation and high speed transmission by researching and developing new high speed interface technology. FPGA has become one of the mainstream platforms to realize digital system. FPGA is widely used in various fields such as signal processing and communication. FPGA can run in parallel in signal processing, and the processing speed is high. But it is not suitable for high precision and complex operation, and PC computer has quite powerful computing and data processing ability. Therefore, the computer is usually responsible for the complex computation with high accuracy, which involves a large amount of data transmission between FPGA and PC. Therefore, the construction of high-speed data transmission system between PC and FPGA has become the current research trend. According to the current research trend and the requirements of the actual scientific research projects, PCIe and Gigabit Ethernet have been deeply studied in this paper. PCIe DMA data transmission system and gigabit Ethernet data transmission system are designed to realize the data communication between FPGA and PC. 1. Deeply study PCIe and Gigabit Ethernet. Understand the technical advantages of PCIe and Gigabit Ethernet, and analyze the transport protocols of PCIe and Gigabit Ethernet. The PCIe TLP data packet format and Ethernet standard data frame format. 2. Complete the design of PCIe DMA data transmission system. The design scheme mainly includes two parts. Verilog logic module development of FPGA, driver of PC and C application development. FPGA-based sending and receiving engine module based on PCIe IP Core. The design of register read-write control module and FIFO read-write control module. The interface of the corresponding module is defined. And analyze the timing of data transmission. PC end using WinDriver to develop the driver of PCIe. According to the driver API function provided by WinDriver, the design of C application program is completed. 3. The design of gigabit Ethernet data transmission system is completed. The design scheme mainly includes two parts. The development of Verilog logic module in FPGA terminal and Winpcap application program in PC terminal. FPGA-based MAC IP Core based on embedded three-state Ethernet. Designed the sending and receiving engine module FIFO read and write control module and physical interface module, and defined the interface of the corresponding module. And analyzed the data transmission through the LocalLink interface and Client user interface transmission timing. PC end using network programming provided by Winpcap to complete the design of C application program. The function of capturing the data packets sent by the FPGA side and sending the original data packets to the FPGA side. 4. PCIe. DMA data transmission system and gigabit Ethernet data transmission system are tested on the Xilinx ML507 development board, and the results of reading and writing test between FPGA and PC are recorded. Verify the availability and stability of the two systems. Finally, the paper analyzes the reasons that affect the transmission rate of the system and the shortcomings of the system at present. The PCIe designed in this paper. DMA data transmission system and gigabit Ethernet data transmission system basically realize the fast data transmission between FPGA and PC. It has made a certain contribution to the follow-up scientific research.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TN915.02

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