本文關(guān)鍵詞：基于FPGA的高效LDPC譯碼器的研究　出處：《北京交通大學(xué)》2014年碩士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： LDPC碼 最小和譯碼器 FPGA 高吞吐量 可配置

【摘要】：摘要：低密度奇偶校驗(yàn)(LDPC)碼是一種近Shannon限高效線性分組碼,已為許多通信標(biāo)準(zhǔn)采納�，F(xiàn)代高速通信對譯碼器速率的要求,使得LDPC碼的硬件譯碼器設(shè)計(jì)與實(shí)現(xiàn)成為LDPC碼研究領(lǐng)域的熱點(diǎn)。FPGA具有并行性和高速運(yùn)行的特點(diǎn),成為LDPC譯碼器的不二之選,本文的工作亦基于FPGA平臺(tái)實(shí)現(xiàn)。在分析比較了LDPC碼的幾種軟判決譯碼算法,綜合考慮了算法的復(fù)雜度和譯碼性能后,選擇了性能優(yōu)異且復(fù)雜度較低的最小和算法作為譯碼器的算法基礎(chǔ)。以此為契機(jī),針對目前LDPC碼硬件譯碼器結(jié)構(gòu)不夠靈活、片上資源消耗偏大的問題,提出了基于最小和算法的兩種高效LDPC譯碼器,并在Xilinx公司的FPGA平臺(tái)上驗(yàn)證。 一種是適用于所有LDPC碼的可配置的譯碼器,它將所有碼都當(dāng)做隨機(jī)碼進(jìn)行處理,對譯碼過程中信息存儲(chǔ)方式的優(yōu)化和流水線的處理方式,在保證吞吐量的前提下,使譯碼器最大限度地減少了片上資源的消耗。分別選擇了準(zhǔn)循環(huán)LDPC碼和隨機(jī)LDPC碼進(jìn)行驗(yàn)證,與傳統(tǒng)的部分譯碼器相比,該譯碼器使用的片上RAM資源比部分譯碼器降低一半以上,同時(shí)吞吐量幾乎保持不變。 另一種則充分利用了準(zhǔn)循環(huán)LDPC碼的特點(diǎn),能夠并行更新校驗(yàn)節(jié)點(diǎn)和變量節(jié)點(diǎn)的高吞吐量譯碼器。在校驗(yàn)節(jié)點(diǎn)更新結(jié)束后,對信息進(jìn)行存儲(chǔ)的同時(shí),通過地址映射對變量節(jié)點(diǎn)進(jìn)行處理,從而消除了變量節(jié)點(diǎn)和校驗(yàn)節(jié)點(diǎn)更新之間的等待時(shí)間,使得譯碼器的吞吐量得到提升。選擇了IEEE802.11ad標(biāo)準(zhǔn)中1/2碼率的LDPC碼字在BPSK調(diào)制模式下進(jìn)行仿真,當(dāng)主頻為100MHz時(shí),得到：200Mbps的吞吐量。與傳統(tǒng)的部分譯碼器相比,吞吐量提高了將近1/3。 為了對譯碼器的譯碼性能進(jìn)行驗(yàn)證,在Xilinx Spartan-6FPGA平臺(tái)上設(shè)計(jì)實(shí)現(xiàn)了LDPC碼仿真系統(tǒng)的全部子模塊,包括編譯碼模塊,高斯噪聲發(fā)生器,信道模擬模塊。仿真結(jié)果表明,硬件譯碼器的性能與Matlab得到的結(jié)果一致。
[Abstract]:Abstract: low density parity check (LDPC) code is a linear block code near Shannon limit performance, has been applied in many communication standards. The requirements of modern high speed communication rate of the decoder, which makes the design and implementation of hardware decoder of LDPC code LDPC code.FPGA has become a hot research field is parallel and high speed characteristics, become the LDPC decoder's choice, the work of this paper is based on the FPGA platform. In the analysis and comparison of several soft decision LDPC decoding algorithm, considering the complexity of the algorithm and the decoding performance, selection of excellent performance and low complexity minimum sum algorithm as the algorithm based decoder. This opportunity in view of the current LDPC hardware decoder structure is not flexible enough, on-chip resource consumption is too large for the problem, propose two efficient LDPC decoder and minimum algorithm based on FPGA, and in Xilinx's flat Verifying on the platform.
A LDPC code is applicable to all configurable decoder, it will be all the code as a random code for processing, processing and optimization of assembly line of information stored in the decoding process, on the premise of ensuring the throughput, the decoder minimizes the on-chip resource consumption. Choose the quasi cyclic LDPC codes and random LDPC code validation, compared with traditional decoder, the decoder uses on-chip RAM resources to reduce more than half part of the decoder, and the throughput remains almost unchanged.
The other is to make full use of the characteristics of quasi cyclic LDPC codes, a high throughput decoder to update the check nodes and variable nodes in parallel. Check node update after the storage of information at the same time, based on the variable node address mapping process, thus eliminating the waiting time between updating the variable nodes and check nodes. The throughput of the decoder are improved. Choose the LDPC code in IEEE802.11ad standard 1/2 rate is simulated in the BPSK modulation mode, when the frequency is 100MHz, 200Mbps throughput. Compared with the traditional part of the decoder, the throughput is increased by nearly 1/3.
In order to verify the decoding performance of the decoder, the design and implementation of all LDPC code simulation module in Xilinx Spartan-6FPGA platform, including the encoding and decoding module, Gauss noise generator, channel simulation module. The simulation results show that the performance of Matlab hardware decoder obtains the same results.

【學(xué)位授予單位】：北京交通大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：TN911.22

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