本文關(guān)鍵詞：數(shù)字陣列雷達(dá)信號(hào)處理機(jī)設(shè)計(jì)與實(shí)現(xiàn)　出處：《電子科技大學(xué)》2015年碩士論文　論文類(lèi)型：學(xué)位論文

  更多相關(guān)文章： 數(shù)字陣列雷達(dá) 雷達(dá)信號(hào)處理 雷達(dá)系統(tǒng)設(shè)計(jì) 脈沖壓縮

【摘要】：數(shù)字陣列雷達(dá)是一種接收和發(fā)射波束都以數(shù)字方式實(shí)現(xiàn)的全數(shù)字相控陣?yán)走_(dá),它是數(shù)字雷達(dá)的重要類(lèi)型。正如在電子系統(tǒng)中數(shù)字技術(shù)正在取代模擬技術(shù)一樣,數(shù)字雷達(dá)正在取代模擬雷達(dá)。數(shù)字雷達(dá)對(duì)來(lái)自?xún)?nèi)部和外部的射頻干擾以及對(duì)溫度和濕度的反應(yīng)不像模擬雷達(dá)那樣敏感,而且價(jià)格也不像后者那樣貴。此外,數(shù)字陣列雷達(dá)可通過(guò)改變程序來(lái)執(zhí)行根本不同的工作模式,這是模擬雷達(dá)無(wú)法實(shí)現(xiàn)的。數(shù)字陣列雷達(dá)的主要構(gòu)成部分有數(shù)字T/R組件、數(shù)字波束形成、大容量高速數(shù)據(jù)傳輸技術(shù)和高效率軟件化信號(hào)處理機(jī)。接收數(shù)字波束形成是把陣列天線(xiàn)輸出的信號(hào)進(jìn)行A/D采樣后送到數(shù)字波束形成器,然后對(duì)接收信號(hào)進(jìn)行復(fù)加權(quán)處理,形成所需波束信號(hào)。此外,數(shù)字陣列雷達(dá)需要一個(gè)高性能的信號(hào)處理機(jī)來(lái)完成時(shí)序生成、任務(wù)控制、校對(duì)處理、波束控制、目標(biāo)追蹤以及顯示處理等工作。所以,數(shù)字波束形成和數(shù)字信號(hào)處理機(jī)在數(shù)字陣列雷達(dá)中起著舉足輕重的作用。本論文結(jié)合某數(shù)字陣列雷達(dá)項(xiàng)目的具體背景和要求,分析研究數(shù)字陣列雷達(dá)信號(hào)處理機(jī)的信號(hào)處理流程、具體實(shí)現(xiàn)方法和性能分析。提出了該數(shù)字陣列雷達(dá)項(xiàng)目的信號(hào)處理方案;同時(shí)對(duì)各個(gè)模塊進(jìn)行具體設(shè)計(jì)以及Matlab和Modelsim仿真分析;最后完成了基于FPGA的硬件實(shí)現(xiàn),用以驗(yàn)證方案的可行性。本論文完成的主要內(nèi)容包括:第一,數(shù)字陣列雷達(dá)信號(hào)處理基本理論方法的研究。主要包括數(shù)字波束形成、雷達(dá)信號(hào)形式、脈沖壓縮(PC)、動(dòng)目標(biāo)顯示(MTI)和動(dòng)目標(biāo)檢測(cè)(MTD)以及恒虛警檢測(cè)(CFAR)。結(jié)合項(xiàng)目特點(diǎn),本論文闡述了各個(gè)部分的理論知識(shí)和常用實(shí)現(xiàn)方法。第二,信號(hào)處理機(jī)系統(tǒng)設(shè)計(jì)和各模塊設(shè)計(jì)、仿真和分析。結(jié)合項(xiàng)目特點(diǎn),設(shè)定數(shù)字陣列雷達(dá)的具體參數(shù),給出系統(tǒng)方案設(shè)計(jì)、仿真以及性能分析。第三,信號(hào)處理機(jī)基于FPGA的硬件實(shí)現(xiàn)。使用Altera公司的StratixⅢEP3SE80F1152I3為主要芯片,采用VHDL語(yǔ)言。對(duì)信號(hào)處理板的組成結(jié)構(gòu)和重要芯片功能作了詳細(xì)介紹,給出各模塊的Signaltap分析儀取圖以驗(yàn)證設(shè)計(jì)的正確性。
[Abstract]:Digital array radar (digital array radar) is an all digital phased array radar that receives and transmit beamforming in digital manner. It is an important type of digital radar. Just as digital technology is replacing analog technology in electronic systems, digital radar is replacing analog radar. Digital radar does not respond to radio frequency interference and temperature and humidity from inside and outside. It is not as sensitive as simulated radar, and the price is not as expensive as the latter. In addition, digital array radar can perform radically different working modes by changing the program, which is impossible for analog radar. The main components of digital array radar include digital T/R module, digital beamforming, high capacity and high speed data transmission technology and high efficiency software signal processor. Receiving digital beamforming is to transmit signals from array antenna to A/D and send it to digital beamformer. Then, the received signal is processed by complex weighting to form the desired beam signal. In addition, digital array radar needs a high-performance signal processor to complete timing generation, task control, collation, beam control, target tracking and display processing. Therefore, digital beamforming and digital signal processor play an important role in digital array radar. Based on the specific background and requirements of a digital array radar project, this paper analyzes and studies the signal processing flow, implementation method and performance analysis of digital array radar signal processor. The signal processing scheme of the digital array radar project is put forward. At the same time, the specific design of each module and the simulation analysis of Matlab and Modelsim are carried out. Finally, the hardware implementation based on FPGA is completed to verify the feasibility of the scheme. The main contents of this paper are as follows: first, the basic theory and method of digital array radar signal processing. It mainly includes digital beamforming, radar signal form, pulse compression (PC), moving target display (MTI) and moving target detection (MTD) and constant false alarm detection (CFAR). According to the characteristics of the project, this paper expounds the theoretical knowledge and the common realization methods of each part. Second, the design of the signal processor system and the design, simulation and analysis of each module. According to the characteristics of the project, the specific parameters of the digital array radar are set, and the design, simulation and performance analysis of the system are given. Third, the signal processor is based on the hardware implementation of FPGA. The Stratix III EP3SE80F1152I3 of Altera company is used as the main chip, and the VHDL language is used. The structure of the signal processing board and the function of the important chip are introduced in detail, and the Signaltap analyzer of each module is given to verify the correctness of the design.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類(lèi)號(hào)】：TN957.51
，

本文編號(hào)：1343259