Deep learning algorithms are the basis of many artificial intelligence applications. Those algorithms are both computationally intensive and memory intensive, making them difficult to deploy on embedded systems. Thus various deep learning accelerators（DLAs） are proposed and applied to achieve better performance and lower power consumption. However, most deep learning accelerators are unable to support multiple data formats. This research proposes the MW-DLA, a deep learning accelerator supportin... 

【文章來(lái)源】：High Technology Letters. 2020,26(02)EI

【文章頁(yè)數(shù)】：7 頁(yè)

【文章目錄】：
0 Introduction
1 Background and motivation
2 Quantification methodology
3 MW-DLA
    3.1 Baseline accelerator architecture
    3.2 Memory layout
    3.3 Multi-precision multiplier
    3.4 Multiple-precision add tree
    3.5 Data packing and unpacking
4 Evaluation
    4.1 Methodology
    4.2 Result
5 Conclusion



本文編號(hào)：3216481