基于指令插入技術(shù)的多核處理器調(diào)試系統(tǒng)關(guān)鍵技術(shù)研究與實(shí)現(xiàn)
發(fā)布時(shí)間：2019-06-24 13:39
【摘要】：大部分智能電子系統(tǒng)都離不開(kāi)啟動(dòng)代碼、操作系統(tǒng)及應(yīng)用程序的開(kāi)發(fā)或移植。隨著信息技術(shù)的飛速發(fā)展,軟件的設(shè)計(jì)復(fù)雜度和調(diào)試難度也越來(lái)越大。大型程序的開(kāi)發(fā)離不開(kāi)良好的處理器硬件調(diào)試的支持,特別是啟動(dòng)代碼和操作系統(tǒng)的調(diào)試更需要處理器本身硬件調(diào)試系統(tǒng)的支持。研究人員已經(jīng)提出了多種調(diào)試技術(shù)和方法,部分技術(shù)已經(jīng)被廣泛應(yīng)用于軟件開(kāi)發(fā)領(lǐng)域,如ICE、調(diào)試代理、軟件仿真等。但這些調(diào)試技術(shù)對(duì)目前主流的多核多線程處理器的支持還存在一些缺陷,尚不夠完善。本文針對(duì)自主X3處理器,采用指令插入方法設(shè)計(jì)實(shí)現(xiàn)了支持多線程的單核調(diào)試支持部件。在單核調(diào)試支持部件的基礎(chǔ)上針對(duì)多核系統(tǒng),提出了一種異步互連結(jié)構(gòu)。并在此基礎(chǔ)上設(shè)計(jì)實(shí)現(xiàn)了自主多核處理器調(diào)試系統(tǒng)。該調(diào)試系統(tǒng)能夠同時(shí)支持處理器Bootloader調(diào)試和操作系統(tǒng)調(diào)試。本文的創(chuàng)新點(diǎn)和主要工作如下:1)基于復(fù)用內(nèi)核流水線指令提交流水站相應(yīng)控制信號(hào)的方法,提出了一套實(shí)現(xiàn)指令地址斷點(diǎn)、指令斷點(diǎn)、數(shù)據(jù)斷點(diǎn)等匹配與處理的技術(shù)方案。由于內(nèi)核流水線采用分支預(yù)測(cè)、指令亂序發(fā)射等技術(shù),在取指流水站依據(jù)指令地址進(jìn)行斷點(diǎn)匹配,必然導(dǎo)致斷點(diǎn)的誤觸發(fā),如何解決這一問(wèn)題是內(nèi)核調(diào)試支持部件設(shè)計(jì)的難點(diǎn)之一。本文提出復(fù)用流水線指令提交站控制信號(hào)并從取指站開(kāi)始逐站傳遞指令地址的方案,解決了指令地址斷點(diǎn)匹配誤觸發(fā)問(wèn)題,避免了復(fù)雜的流水線行為分析問(wèn)題,使得本設(shè)計(jì)方案具有良好的通用性,適用于各種具有指令順序提交特征的處理器。2)基于指令插入方法設(shè)計(jì)實(shí)現(xiàn)了單個(gè)內(nèi)核的調(diào)試支持部件(DSU)。該部件設(shè)計(jì)方案利用內(nèi)核本身的流水線并針對(duì)調(diào)試加以部件改造,以較少的硬件代價(jià)實(shí)現(xiàn)了對(duì)流水線的運(yùn)行控制、指令插入等操作,使得DSU能夠接收來(lái)自宿主機(jī)的調(diào)試命令,執(zhí)行程序停頓/運(yùn)行控制、指令斷點(diǎn)和數(shù)據(jù)斷點(diǎn)設(shè)置、硬件斷點(diǎn)和軟件斷點(diǎn)設(shè)置、變量查看與更新等多種復(fù)雜的調(diào)試操作。3)提出了一種片上異步互連協(xié)議——CLB,基于CLB構(gòu)建了自主多核處理器X3的調(diào)試系統(tǒng)。設(shè)計(jì)實(shí)現(xiàn)了針對(duì)X3處理器的調(diào)試命令接口協(xié)議和部件,將來(lái)自片外ICE的調(diào)試命令轉(zhuǎn)換為DSU接口報(bào)文,并傳遞到目標(biāo)內(nèi)核。宿主機(jī)調(diào)試軟件采用了開(kāi)源的eclipse和GDB調(diào)試器,實(shí)現(xiàn)了圖形化的交叉調(diào)試環(huán)境。
[Abstract]:Most intelligent electronic systems can not be separated from startup code, operating system and application development or transplantation. With the rapid development of information technology, the design complexity and debugging difficulty of software are becoming more and more difficult. The development of large programs can not be separated from the support of good processor hardware debugging, especially the debugging of startup code and operating system needs the support of processor's own hardware debugging system. Researchers have put forward a variety of debugging techniques and methods, some of which have been widely used in the field of software development, such as ICE, debugging agent, software simulation and so on. However, there are still some defects in the support of these debugging technologies for the current mainstream multi-core multi-thread processor, which is not perfect enough. In this paper, a single core debugging support component supporting multithreading is designed and implemented by using instruction insertion method for autonomous X3 processor. An asynchronous interconnection structure for multi-core systems is proposed on the basis of single-core debugging support components. On this basis, an autonomous multi-core processor debugging system is designed and implemented. The debugging system can support processor Bootloader debugging and operating system debugging at the same time. The innovation and main work of this paper are as follows: 1) based on the method of reusing the kernel pipeline instruction to submit the corresponding control signal of the flow station, a set of technical schemes to realize the matching and processing of instruction address breakpoint, instruction breakpoint, data breakpoint and so on are proposed. Because the kernel pipeline adopts the technology of branch prediction and instruction random sequence transmission, matching the breakpoint according to the instruction address in the fetch flow water station will inevitably lead to the false trigger of the breakpoint. How to solve this problem is one of the difficulties in the design of kernel debugging support components. In this paper, a scheme of reusing pipeline instruction submission station control signal and transmitting instruction address station by station is proposed, which solves the problem of false trigger of instruction address breakpoint matching, avoids the complex problem of pipeline behavior analysis, and makes the design scheme have good generality. It is suitable for all kinds of processors with instruction sequence submission characteristics. 2) the debugging support component (DSU). Of a single kernel is designed and implemented based on instruction insertion method. The component design scheme makes use of the pipeline of the kernel itself and modifies the parts for debugging, and realizes the operation of pipeline operation control and instruction insertion at less hardware cost, so that DSU can receive debugging commands from host computer, execute program pause / operation control, instruction breakpoint and data breakpoint setting, hardware breakpoint and software breakpoint setting. A variety of complex debugging operations, such as variable viewing and updating, are proposed. 3) an on-chip asynchronous interconnection protocol, CLB, is proposed to construct a debugging system of autonomous multi-core processor X3 based on CLB. The debugging command interface protocol and components for X3 processor are designed and implemented. The debugging commands from off-chip ICE are converted into DSU interface messages and passed to the target kernel. The host debugging software adopts open source eclipse and GDB debugger to realize graphical cross-debugging environment.
【學(xué)位授予單位】：國(guó)防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP332
，
本文編號(hào)：2505100
[Abstract]:Most intelligent electronic systems can not be separated from startup code, operating system and application development or transplantation. With the rapid development of information technology, the design complexity and debugging difficulty of software are becoming more and more difficult. The development of large programs can not be separated from the support of good processor hardware debugging, especially the debugging of startup code and operating system needs the support of processor's own hardware debugging system. Researchers have put forward a variety of debugging techniques and methods, some of which have been widely used in the field of software development, such as ICE, debugging agent, software simulation and so on. However, there are still some defects in the support of these debugging technologies for the current mainstream multi-core multi-thread processor, which is not perfect enough. In this paper, a single core debugging support component supporting multithreading is designed and implemented by using instruction insertion method for autonomous X3 processor. An asynchronous interconnection structure for multi-core systems is proposed on the basis of single-core debugging support components. On this basis, an autonomous multi-core processor debugging system is designed and implemented. The debugging system can support processor Bootloader debugging and operating system debugging at the same time. The innovation and main work of this paper are as follows: 1) based on the method of reusing the kernel pipeline instruction to submit the corresponding control signal of the flow station, a set of technical schemes to realize the matching and processing of instruction address breakpoint, instruction breakpoint, data breakpoint and so on are proposed. Because the kernel pipeline adopts the technology of branch prediction and instruction random sequence transmission, matching the breakpoint according to the instruction address in the fetch flow water station will inevitably lead to the false trigger of the breakpoint. How to solve this problem is one of the difficulties in the design of kernel debugging support components. In this paper, a scheme of reusing pipeline instruction submission station control signal and transmitting instruction address station by station is proposed, which solves the problem of false trigger of instruction address breakpoint matching, avoids the complex problem of pipeline behavior analysis, and makes the design scheme have good generality. It is suitable for all kinds of processors with instruction sequence submission characteristics. 2) the debugging support component (DSU). Of a single kernel is designed and implemented based on instruction insertion method. The component design scheme makes use of the pipeline of the kernel itself and modifies the parts for debugging, and realizes the operation of pipeline operation control and instruction insertion at less hardware cost, so that DSU can receive debugging commands from host computer, execute program pause / operation control, instruction breakpoint and data breakpoint setting, hardware breakpoint and software breakpoint setting. A variety of complex debugging operations, such as variable viewing and updating, are proposed. 3) an on-chip asynchronous interconnection protocol, CLB, is proposed to construct a debugging system of autonomous multi-core processor X3 based on CLB. The debugging command interface protocol and components for X3 processor are designed and implemented. The debugging commands from off-chip ICE are converted into DSU interface messages and passed to the target kernel. The host debugging software adopts open source eclipse and GDB debugger to realize graphical cross-debugging environment.
【學(xué)位授予單位】：國(guó)防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP332
，
本文編號(hào)：2505100
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