【摘要】：快速傅里葉變換廣泛地應用于數(shù)字信號處理(DSP),尤其是二維快速傅里葉變換(2D-FFT)在成像技術的光譜和頻域分析中有重要的應用,如圖像數(shù)字水印、指紋識別、合成孔徑雷達成像處理以及醫(yī)學成像等。隨著所需處理的數(shù)字信號量的增加,對2D-FFT性能和實時性的要求也越來越高。目前2D-FFT算法的實現(xiàn)多局限于專用集成電路與DSP,但這兩種實現(xiàn)方式都存在著某種不足。當前,為滿足應用需求,彌補前兩種實現(xiàn)方式的不足,采用速度更快、重構性好的FPGA實現(xiàn)具有并行特征的2D-FFT算法,己成為國內外研究的熱點。 本設計追逐熱點研究,探索在FPGA上實現(xiàn)高性能的2D-FFT處理器,并將所設計的2D-FFT處理單元封裝成IP核,采用自定義組件的方式添加進SOPC系統(tǒng)中,并添加相關的系統(tǒng)組件如Nios Ⅱ軟核、SDRAM等來實現(xiàn)一個可裁剪、可擴充、可升級的2D-FFT處理系統(tǒng)。在FPGA底層設計中,采用蝶形單元與CORDIC算法設計實現(xiàn)FFT處理單元,并采用乒乓倒換的方式實現(xiàn)矩陣轉置,再用這兩個關鍵模塊組合成所需的2D-FFT處理模塊,參照最新Avalon總線標準對其進行模塊封裝以利于采用自定義組件方法集成進SOPC系統(tǒng)。 該系統(tǒng)在Quartus Ⅱ8.0開發(fā)平臺中進行最終的布局布線,經過專業(yè)仿真工且ModelSim進行仿真和測試后,下載到Altera公司的所提供的開發(fā)板DE2上進行實物驗證。并將最終實物驗證結果與Matlab函數(shù)處理結果來對比,最后結果表明本設計具有運行穩(wěn)定,速度快,占用資源少等優(yōu)點,具有很好的應用前景。
[Abstract]:Fast Fourier transform is widely used in digital signal processing (DSP), especially two-dimensional fast Fourier transform (2D-FFT), which has important applications in spectral and frequency domain analysis of imaging technology, such as image digital watermarking, fingerprint recognition. Synthetic aperture radar imaging processing and medical imaging. With the increase of digital semaphores to be processed, the performance and real-time requirements of 2D-FFT are getting higher and higher. At present, the implementation of 2D-FFT algorithm is mostly limited to ASIC and DSP, but there are some shortcomings in these two implementation methods. At present, in order to meet the application requirements and make up for the shortcomings of the first two implementation methods, the implementation of 2D-FFT algorithm with parallel characteristics by using FPGA with faster speed and good reconstruction has become a hot research topic at home and abroad. This design pursues the hot research, explores the implementation of high performance 2D-FFT processor on FPGA, and encapsulates the designed 2D-FFT processing unit into IP core, which is added to the SOPC system by means of custom components. The related system components such as Nios II soft core, SDRAM and so on are added to realize a clipped, extensible and upgraded 2D-FFT processing system. In the bottom design of FPGA, the butterfly element and CORDIC algorithm are used to design and implement the FFT processing unit, and the ping-pong switching method is used to realize the matrix transposition, and then the two key modules are combined into the required 2D-FFT processing module. According to the latest Avalon bus standard, the module encapsulation is carried out to facilitate the integration of custom component method into SOPC system. The final layout and routing of the system is carried out in Quartus 鈪，

本文編號：2491044