天文圖像差異算法專用硬件設(shè)計與SOC實現(xiàn)
發(fā)布時間：2019-05-15 20:42
【摘要】：隨著處理器技術(shù)的飛速發(fā)展,微處理器在一定程度上有了很大的應(yīng)用范圍,而可配置處理器可以對具體應(yīng)用進(jìn)行適當(dāng)配置,從而可以得到不同運算模塊的硬件電路。通過對其進(jìn)行編程管理,達(dá)到最終功能的實現(xiàn)。用可配置處理器完成數(shù)據(jù)密集型的運算任務(wù)時,比通用微處理器具有更強(qiáng)的計算能力,比ASIC(Application Specific Integrated Circuit)架構(gòu)具有更大的靈活性,可加快研發(fā)周期,同時在功耗方面低于通用數(shù)字信號處理器。本論文設(shè)計了一個面向天文圖像差異算法的可配置處理器—傳輸觸發(fā)架構(gòu)(TTA,Transport-Triggered Architecture)的T*Core模型。選擇應(yīng)用之后,根據(jù)配置相關(guān)的參數(shù)就可生成一款針對特定領(lǐng)域的T*Core處理器的硬件電路。 本論文對天文圖像差異算法進(jìn)行詳細(xì)的歸納與分析,對降晰函數(shù),核函數(shù)以及相關(guān)的求解方法,不同天空背景環(huán)境下的情況進(jìn)行分析處理。這些分析,為T*Core處理器的功能單元設(shè)計提供算法的依據(jù),T*Core的結(jié)構(gòu)包含整體架構(gòu)設(shè)計、內(nèi)部核心單元、指令格式、流水線、網(wǎng)絡(luò)通路、存儲器和最終的系統(tǒng)編址等。其中基于算法的功能單元是影響整個處理器的關(guān)鍵部件,對數(shù)據(jù)處理的實時性起關(guān)鍵作用,有效合理的對其優(yōu)化,更可以提高系統(tǒng)整體的速度。 在硬件驗證中,本論文利用XILINX FPGA的XUPV5-LX110T系列MACROBLAZE作為主處理器,T*Core為協(xié)處理器,搭建一個嵌入式SOC(System on Chip)開發(fā)系統(tǒng)。通過SOC實現(xiàn)后,系統(tǒng)頻率最終跑到100M以上。T*Core處理器的硬件架構(gòu)設(shè)計已經(jīng)通過了前期的仿真、驗證及最后的板級系統(tǒng)調(diào)試。為了進(jìn)一步提高速度,本文采用多核異構(gòu)T*Core處理器的并行處理方案,這可以充分發(fā)揮T*Core處理器的數(shù)據(jù)密集型運算的特點。通過最后的SOC實現(xiàn),T*Core處理器和普通的PC機(jī)軟件實現(xiàn)相比,在功能正確的基礎(chǔ)上,計算速度得到有效提高。功耗得到大大降低,雙核功耗僅為軟件實現(xiàn)時的2.3%。通過這種架構(gòu)實現(xiàn),再次證明了T*Core處理器可以達(dá)到實時性和低功耗的要求。
[Abstract]:With the rapid development of processor technology, microprocessors have a wide range of applications to a certain extent, and the configurable processor can properly configure the specific applications, so that the hardware circuits of different operation modules can be obtained. Through the programming management, to achieve the final function of the realization. When using a configurable processor to complete data-intensive computing tasks, it has stronger computing power than a general-purpose microprocessor, has greater flexibility than the ASIC (Application Specific Integrated Circuit) architecture, and can speed up the research and development cycle. At the same time, the power consumption is lower than that of the general digital signal processor. In this paper, a T*Core model of transmission trigger architecture (TTA,Transport-Triggered Architecture) for astronomical image difference algorithm is designed. After selecting the application, a domain-specific T*Core processor hardware circuit can be generated according to the configuration-related parameters. In this paper, the astronomical image difference algorithm is summarized and analyzed in detail, and the blurring function, kernel function and related solving methods are analyzed and processed in different sky background environment. These analyses provide the basis for the functional unit design of T*Core processor. The structure of T*Core includes the overall architecture design, internal core unit, instruction format, pipeline, network path, memory and final system addressing. Among them, the functional unit based on the algorithm is the key component that affects the whole processor, which plays a key role in the real-time performance of data processing. The effective and reasonable optimization of the function unit can improve the overall speed of the system. In the hardware verification, this paper uses XUPV5-LX110T series MACROBLAZE of XILINX FPGA as the main processor and T*Core as the coprocessor to build an embedded SOC (System on Chip) development system. After the implementation of SOC, the frequency of the system finally runs above 100m. The hardware architecture design of T * Core processor has passed the previous simulation, verification and final board level system debugging. In order to further improve the speed, this paper adopts the parallel processing scheme of multi-core heterogeneous T*Core processor, which can give full play to the characteristics of data-intensive operation of T*Core processor. Through the final SOC implementation, compared with the ordinary PC software implementation, the calculation speed of T*Core processor is effectively improved on the basis of correct function. The power consumption is greatly reduced, and the dual-core power consumption is only 2.3% of that of the software. Through this architecture, it is proved that T*Core processor can meet the requirements of real-time and low power consumption.
【學(xué)位授予單位】：天津大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2012
【分類號】：TP332;TP368.1
本文編號：2477742
[Abstract]:With the rapid development of processor technology, microprocessors have a wide range of applications to a certain extent, and the configurable processor can properly configure the specific applications, so that the hardware circuits of different operation modules can be obtained. Through the programming management, to achieve the final function of the realization. When using a configurable processor to complete data-intensive computing tasks, it has stronger computing power than a general-purpose microprocessor, has greater flexibility than the ASIC (Application Specific Integrated Circuit) architecture, and can speed up the research and development cycle. At the same time, the power consumption is lower than that of the general digital signal processor. In this paper, a T*Core model of transmission trigger architecture (TTA,Transport-Triggered Architecture) for astronomical image difference algorithm is designed. After selecting the application, a domain-specific T*Core processor hardware circuit can be generated according to the configuration-related parameters. In this paper, the astronomical image difference algorithm is summarized and analyzed in detail, and the blurring function, kernel function and related solving methods are analyzed and processed in different sky background environment. These analyses provide the basis for the functional unit design of T*Core processor. The structure of T*Core includes the overall architecture design, internal core unit, instruction format, pipeline, network path, memory and final system addressing. Among them, the functional unit based on the algorithm is the key component that affects the whole processor, which plays a key role in the real-time performance of data processing. The effective and reasonable optimization of the function unit can improve the overall speed of the system. In the hardware verification, this paper uses XUPV5-LX110T series MACROBLAZE of XILINX FPGA as the main processor and T*Core as the coprocessor to build an embedded SOC (System on Chip) development system. After the implementation of SOC, the frequency of the system finally runs above 100m. The hardware architecture design of T * Core processor has passed the previous simulation, verification and final board level system debugging. In order to further improve the speed, this paper adopts the parallel processing scheme of multi-core heterogeneous T*Core processor, which can give full play to the characteristics of data-intensive operation of T*Core processor. Through the final SOC implementation, compared with the ordinary PC software implementation, the calculation speed of T*Core processor is effectively improved on the basis of correct function. The power consumption is greatly reduced, and the dual-core power consumption is only 2.3% of that of the software. Through this architecture, it is proved that T*Core processor can meet the requirements of real-time and low power consumption.
【學(xué)位授予單位】：天津大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2012
【分類號】：TP332;TP368.1
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