基于FPGA的數(shù)據(jù)高速非易失存儲技術(shù)研究
[Abstract]:In modern war, damage effect evaluation, as an important combat task, plays a decisive role in decision-making and strategic decision-making of war situation. It is an important task to obtain high-resolution and large field-of-view images as far as possible because it is the most direct-viewing image to reflect the damage effect. With the rapid development of imaging technology, the resolution of imaging is getting higher and higher, and the frame rate is getting faster and faster. It is difficult to recover a large amount of experimental data by wireless mode. Therefore, the detection system usually uses high-speed and large-capacity non-volatile memory to store high-speed real-time image data or radar signal, and then read back the data to the computer for data analysis. Especially in the worse conditions, the high-speed and large-capacity storage of high-definition images requires higher performance of storage devices. First, the storage rate is high, the storage speed must meet the transmission rate of data sampling; the second is the large storage capacity, high-speed data acquisition will inevitably produce a large number of data streams; third, the reliability of data storage devices is high. Storage devices can not only work in harsh environment, but also ensure the correctness of stored data. In addition, memory structure size, impact resistance, power consumption and so on are also important considerations. Therefore, it is very important to develop a large-capacity solid-state storage system with small size, high-order shock and temperature shock, low power consumption, light weight and low cost in wireless detection equipment. In this paper, the hardware architecture and system implementation scheme of high-speed and large-capacity data storage in limited size space are introduced. In this design, a piece of FPGA is used as the core controller and the hardware structure of two NANDFLASH chips is controlled at the same time. According to the characteristics of double CE and page programming of the flash chip, the ping-pong pipelining control technology is introduced to realize the real-time and high-speed storage of the data. At the same time, the bad block list information is set up, which shields the bad block address of the flash chip and ensures the stable operation of the storage system. When the data is read back, the data of the memory card is read back to the computer by using the most communication bridge of the single card reader. This paper also introduces the hardware working mechanism of the card reader, the bad block management software, the conversion image software and the design method of the card reader application software. Finally, the system is summarized and prospected.
【學(xué)位授予單位】:電子科技大學(xué)
【學(xué)位級別】:碩士
【學(xué)位授予年份】:2013
【分類號】:TP333
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