低成本的USB2.0主機控制器與驅(qū)動程序設(shè)計
發(fā)布時間：2019-04-27 00:56
【摘要】：由于USB具有傳輸速度快,支持熱插拔,使用靈活等優(yōu)良特性,已經(jīng)成為一種應(yīng)用非常廣泛的串行接口標(biāo)準,差不多有電子設(shè)備的地方就有USB。正因為如此,有不少企業(yè)或研究單位,投入大量的人力與物力,參入到USB相關(guān)的硬件與軟件的研究與開發(fā),期望在自己的產(chǎn)品中加入USB的功能,以提高產(chǎn)品的競爭力,除了要達到所需的USB性能,還不能增加太多的成本。于是提出了開發(fā)低成本USB2.0主機控制器的課題。 本論文首先討論了USB2.0與UTMI等相關(guān)的協(xié)議,然后分析了市場上主要幾類主機控制器(UHCI、OHCI、EHCI、xHCI和其它廠商或個人自行定義的)及相關(guān)協(xié)議標(biāo)準或硬件與軟件設(shè)計方案。并以此為基礎(chǔ),提出新的低成本的USB2.0主機控制器的硬件與軟件設(shè)計方案。 硬件設(shè)計方案部分包含USB2.0主機控制器的架構(gòu),軟硬件寄存器接口定義及AHB從機接口模塊(usb20_sl_if)、DMA控制模塊(usb20_dma_ctl)、緩沖管理模塊(buffer_manage)、協(xié)議層控制模塊(usb20_host_pl)、主機寄存器模塊(usb20_host_reg)、集線器控制模塊(usb20_port_ctl)等各功能子模塊功能及狀態(tài)轉(zhuǎn)換描述,并用Verilog HDL實現(xiàn)。 軟件設(shè)計方案部分,只設(shè)計了與硬件相關(guān)的主機控制器驅(qū)動程序部分,與硬件無關(guān)的USB協(xié)議棧與客戶端軟件可以直接復(fù)用Linux內(nèi)核中的相關(guān)程序。主機控制器驅(qū)動程序包含了USBD接口模塊、根集線器模塊、數(shù)據(jù)傳輸模塊、中斷管理模塊等子模塊功能及函數(shù)描述,并用C語言實現(xiàn)。 此外還定性分析了此方案確實會比UHCI、 OHCI、 EHCI、xHCI等主機控制器的硬件成本低,也定性分析了此方案在存儲類設(shè)備方面的性能不會遜色于UHCI、 OHCI、 EHCI、xHCI等主機控制器。為了保證此方案的主機控制器的高性能,實現(xiàn)了兩點創(chuàng)新：一是用兩個單端口SRAM來實現(xiàn)異步時鐘域的乒乓緩沖；二是利用DMA讀寫數(shù)據(jù)傳輸與USB傳輸?shù)牧魉�并行操作,從而提高USB總線的帶寬利用率或降低對系統(tǒng)總線的帶寬的要求。 最后采用基于BFM的自動化的驗證方法,對USB2.0主機控制器的低速、全速、高速的數(shù)據(jù)傳輸,總線復(fù)位及DMA等相關(guān)模式及操作做了完整的驗證,都符合USB2.0及UTMI協(xié)議標(biāo)準。同時還用Synopsys的Design Compile綜合工具,對USB2.0主機控制器的RTL綜合出來的電路只有7.5千門(不包含SRAM面積)。結(jié)果表明,此方案是可行的,能同時滿足低成本高性能的需求,達到了預(yù)期的目標(biāo)。
[Abstract]:USB has become a very widely used serial interface standard because of its high transmission speed, hot-swappable support, flexible use, and so on. There is USB. almost where there are electronic devices. Because of this, many enterprises or research institutions have invested a great deal of manpower and material resources in the research and development of hardware and software related to USB, hoping to add the function of USB in their own products, in order to improve the competitiveness of their products. In addition to achieving the required USB performance, there is not much to add to the cost. Therefore, the subject of developing low-cost USB2.0 host controller is put forward. This paper first discusses the protocols related to USB2.0 and UTMI, and then analyzes the main types of host controllers (defined by UHCI,OHCI,EHCI,xHCI and other manufacturers or individuals) in the market as well as related protocol standards or hardware and software design schemes. Based on this, a new hardware and software design scheme of low-cost USB2.0 host controller is proposed. The hardware design includes USB2.0 host controller architecture, hardware and software register interface definition and AHB slave interface module (usb20_sl_if), DMA control module (usb20_dma_ctl), buffer management module (buffer_manage). Protocol layer control module (usb20_host_pl), host register module (usb20_host_reg), hub control module (usb20_port_ctl) and other functional sub-modules function and state transition description, and implemented with Verilog HDL. In the software design part, only the hardware-related host controller driver is designed. The hardware-independent USB protocol stack and the client software can directly reuse the related programs in the Linux kernel. Host controller driver includes USBD interface module, root hub module, data transmission module, interrupt management module and other sub-module functions and function description, and implemented in C language. In addition, the hardware cost of this scheme is lower than that of UHCI, OHCI, EHCI,xHCI and other host controllers, and the performance of this scheme is not inferior to that of UHCI, OHCI, EHCI,xHCI and other host controllers. In order to ensure the high performance of the host controller, two innovations are realized: one is to use two single-port SRAM to realize the ping-pong buffer of asynchronous clock domain; The other is to use the pipelined parallel operation of DMA read-write data transmission and USB transmission, so as to improve the bandwidth utilization of USB bus or reduce the requirement of system bus bandwidth. Finally, the automatic verification method based on BFM is used to verify the low-speed, full-speed, high-speed data transmission, bus reset, DMA and other related modes and operations of the USB2.0 host controller. All of them conform to the standards of USB2.0 and UTMI protocol. At the same time, using the Design Compile synthesis tool of Synopsys, only 7.5 thousand gates (excluding the SRAM area) are integrated from the RTL of the USB2.0 host controller. The results show that this scheme is feasible and can meet the requirements of low-cost and high-performance at the same time.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2012
【分類號】：TP332.3
本文編號：2466544
[Abstract]:USB has become a very widely used serial interface standard because of its high transmission speed, hot-swappable support, flexible use, and so on. There is USB. almost where there are electronic devices. Because of this, many enterprises or research institutions have invested a great deal of manpower and material resources in the research and development of hardware and software related to USB, hoping to add the function of USB in their own products, in order to improve the competitiveness of their products. In addition to achieving the required USB performance, there is not much to add to the cost. Therefore, the subject of developing low-cost USB2.0 host controller is put forward. This paper first discusses the protocols related to USB2.0 and UTMI, and then analyzes the main types of host controllers (defined by UHCI,OHCI,EHCI,xHCI and other manufacturers or individuals) in the market as well as related protocol standards or hardware and software design schemes. Based on this, a new hardware and software design scheme of low-cost USB2.0 host controller is proposed. The hardware design includes USB2.0 host controller architecture, hardware and software register interface definition and AHB slave interface module (usb20_sl_if), DMA control module (usb20_dma_ctl), buffer management module (buffer_manage). Protocol layer control module (usb20_host_pl), host register module (usb20_host_reg), hub control module (usb20_port_ctl) and other functional sub-modules function and state transition description, and implemented with Verilog HDL. In the software design part, only the hardware-related host controller driver is designed. The hardware-independent USB protocol stack and the client software can directly reuse the related programs in the Linux kernel. Host controller driver includes USBD interface module, root hub module, data transmission module, interrupt management module and other sub-module functions and function description, and implemented in C language. In addition, the hardware cost of this scheme is lower than that of UHCI, OHCI, EHCI,xHCI and other host controllers, and the performance of this scheme is not inferior to that of UHCI, OHCI, EHCI,xHCI and other host controllers. In order to ensure the high performance of the host controller, two innovations are realized: one is to use two single-port SRAM to realize the ping-pong buffer of asynchronous clock domain; The other is to use the pipelined parallel operation of DMA read-write data transmission and USB transmission, so as to improve the bandwidth utilization of USB bus or reduce the requirement of system bus bandwidth. Finally, the automatic verification method based on BFM is used to verify the low-speed, full-speed, high-speed data transmission, bus reset, DMA and other related modes and operations of the USB2.0 host controller. All of them conform to the standards of USB2.0 and UTMI protocol. At the same time, using the Design Compile synthesis tool of Synopsys, only 7.5 thousand gates (excluding the SRAM area) are integrated from the RTL of the USB2.0 host controller. The results show that this scheme is feasible and can meet the requirements of low-cost and high-performance at the same time.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2012
【分類號】：TP332.3
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