【摘要】：數(shù)據(jù)中心以可接受的成本,承載著超大規(guī)模的互聯(lián)網(wǎng)應(yīng)用.數(shù)據(jù)中心的能源消耗直接影響著數(shù)據(jù)中心的一次性建造成本和長期維護(hù)成本,是數(shù)據(jù)中心總體持有成本的重要組成部分.現(xiàn)代的數(shù)據(jù)中心普遍采用動態(tài)電壓頻率調(diào)節(jié)(dynamic voltage frequency scaling,簡稱DVFS)來提升單節(jié)點(diǎn)的能耗表現(xiàn).但是,DVFS這一類機(jī)制同時影響到應(yīng)用的能源消耗和性能,而這一問題尚未被深入探索.專注于DVFS機(jī)制對應(yīng)用程序性能的影響,提出了一個分析模型用來量化地刻畫應(yīng)用程序的性能與處理器頻率之間的關(guān)系,可以預(yù)測程序在任意頻率下的性能.具體來說,依據(jù)執(zhí)行時訪問內(nèi)存子系統(tǒng)資源的不同,把程序的指令分為兩部分——片上指令和片外指令,并分別獨(dú)立建模.片上指令是指僅需訪問片上資源就可以完成執(zhí)行的指令,其執(zhí)行時間與處理器頻率呈線性關(guān)系;片外指令是指需要訪問主存的指令,其執(zhí)行時間與處理器頻率無關(guān).通過上述劃分和對每一部分執(zhí)行時間的分別建模,可以獲得應(yīng)用程序的執(zhí)行時間與處理器頻率之間的量化模型.使用兩個不同的平臺和SPEC 2006中的所有標(biāo)準(zhǔn)程序驗(yàn)證該模型,平均誤差不超過1.34%.
[Abstract]:Data centers carry ultra-large-scale Internet applications at an acceptable cost. The energy consumption of the data center directly affects the one-time construction cost and the long-term maintenance cost of the data center, and it is an important part of the total holding cost of the data center. Dynamic voltage frequency regulation (dynamic voltage frequency scaling,) is widely used in modern data centers to improve the performance of single node energy consumption. However, such mechanisms as DVFS affect the energy consumption and performance of applications at the same time, and this problem has not been deeply explored. Focusing on the effect of DVFS mechanism on application performance, an analytical model is proposed to quantitatively describe the relationship between application performance and processor frequency, which can predict the performance of applications at any frequency. Specifically, according to the different resources of accessing memory subsystem during execution, the instruction of the program is divided into two parts-on-chip instruction and out-of-chip instruction, and is modeled independently. On-chip instruction refers to instructions that can be executed only by accessing on-chip resources, and its execution time is linearly related to processor frequency, while out-of-chip instructions refer to instructions that need to access main memory, and their execution time is independent of processor frequency. The quantization model between the execution time of the application and the frequency of the processor can be obtained by the above partition and the modeling of each part of the execution time. The model was validated using two different platforms and all the standard programs in SPEC 2006 with an average error of not more than 1.34%.
【作者單位】： 計算機(jī)體系結(jié)構(gòu)國家重點(diǎn)實(shí)驗(yàn)室(中國科學(xué)院計算技術(shù)研究所);中國科學(xué)院大學(xué)計算機(jī)控制與工程學(xué)院;
【基金】：國家重點(diǎn)基礎(chǔ)研究發(fā)展計劃(973)(2016YFB1000402) 國家高技術(shù)研究發(fā)展計劃(863)(2015AA015306) 國家自然科學(xué)基金(61672492,61432016,61402445,61521092)~~
【分類號】：TP308

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