【摘要】：隨著集成電路的迅速發(fā)展,人們對于處理器的性能要求也越來越高,尤其在數值計算方面,既要求能夠保證足夠的速度和精度,又希望能有效的控制硬件面積和功耗。浮點數據的計算已經成為大多數處理器的基本要求,除了需要完成簡單的浮點加法、減法和乘法運算以外,還要求能夠完成一些初等函數運算,例如倒數、平方根、平方根倒數、指數、對數等等。 本文主要研究的是在單精度浮點數領域的初等函數運算器低成本設計,比較適用于移動設備中。通過對初等函數實現方法的研究,基于查找表的分段多項式逼近方法是目前單精度初等函數逼近最理想的方法,它不但在查找表面積與計算速度兩方面做了很好的平衡,而且能夠實現絕大多數的初等函數運算。 本文利用相鄰區(qū)間參數約束的理論,在不造成過大誤差的前提下,有效地減少了多項式逼近中所需要存儲的參數數量,并且通過MILP(混合整型規(guī)劃)問題優(yōu)化誤差。在二次多項式運算部分,利用乘法分配率進行形式變換,將一次平方運算、兩次乘法運算和三次加法運算轉化為兩次乘加運算,并通過復用乘加結構完成運算。對于華萊士樹進行截斷處理,有效減少了硬件邏輯。結果證明總的運算部分的面積能夠減少40%,包括查找表和多項式計算兩部分。同時針對浮點格式數據,本文還加入了預處理和后處理模塊,整個設計在SMIC0.18um工藝下進行綜合,時鐘頻率可以達到300MHz,而面積為0.22mm2。
[Abstract]:With the rapid development of integrated circuits, the performance requirements of processors become higher and higher, especially in numerical computation, not only to ensure sufficient speed and accuracy, but also to control the hardware area and power consumption effectively. Floating-point data calculation has become the basic requirement of most processors, in addition to the need to complete simple floating-point addition, subtraction and multiplication, but also to be able to complete some elementary function operations, such as reciprocal, square root, Square-root reciprocal, exponent, logarithm, etc. This paper focuses on the low-cost design of elementary function operators in the field of single-precision floating-point numbers, which is more suitable for mobile devices. Through the research on the realization method of elementary function, the piecewise polynomial approximation method based on look-up table is the most ideal method for single-precision elementary function approximation at present. It not only makes a good balance between the search surface area and the calculation speed, but also has a good balance between the searching surface area and the computing speed. And can realize the vast majority of elementary function operation. In this paper, the theory of parameter constraints in adjacent interval is used to reduce effectively the number of parameters stored in polynomial approximation without causing too much error, and the optimization error of MILP (mixed integral programming) problem is adopted. In the second order polynomial operation part, the multiplicative distribution rate is used to carry on the formal transformation, the first square operation, the two times multiplication operation and the three times addition operation are transformed into the two times multiplication and addition operation, and the operation is completed by the multiplex multiplication and addition structure. The hardware logic is effectively reduced by truncating the Wallace tree. The results show that the total area of the operation can be reduced by 40%, including lookup table and polynomial calculation. At the same time, the pre-processing and post-processing modules are added to the floating-point format data. The whole design is synthesized in SMIC0.18um process. The clock frequency can reach 300 MHz and the area is 0.22 Mm2.
【學位授予單位】：浙江大學
【學位級別】：碩士
【學位授予年份】：2013
【分類號】：TP332.2

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本文編號：2459837