【摘要】：靜態(tài)隨機訪問存儲器（SRAM）作為最重要的半導(dǎo)體存儲器，廣泛地嵌入于高性能微處理器。隨著集成電路制造工藝的不斷提升，存儲器占據(jù)芯片的功耗比例越來越大，高速低功耗的SRAM設(shè)計變得越來越重要。 本文結(jié)合全定制設(shè)計、基于標準單元設(shè)計而通過人工布局布線實現(xiàn)的半定制設(shè)計流程，對高速低功耗SRAM的設(shè)計、實現(xiàn)與驗證技術(shù)進行了研究，具體包括： （1）65nm工藝下高速SRAM的設(shè)計與實現(xiàn) SRAM基于帶異步復(fù)位端的13管1W/1R存儲單元，具有較高的讀操作穩(wěn)定性和較低的漏電流，但它的寫入延時和版圖面積大。為了彌補這些缺陷，針對雙位線的寫入結(jié)構(gòu)，本文提出了位線共享的低功耗位線策略。讀譯碼和數(shù)據(jù)讀出通路以犧牲面積和功耗獲得了更快的讀出速度，這使得實現(xiàn)的SRAM與MemoryCompiler生成的相同容量的SRAM相比，，輸出延時減小了41.62%。在實現(xiàn)方式上，SRAM的外圍電路采用標準單元設(shè)計而通過人工布局布線實現(xiàn)，縮短了設(shè)計周期。本文運用腳本語言開發(fā)了具有高仿真精度的電路和版圖的自動化驗證流程。 （2）40nm工藝下高速低功耗SRAM的設(shè)計與實現(xiàn) SRAM基于10管1W/2R存儲單元，采用了兩級動態(tài)譯碼、層次的動態(tài)預(yù)充的讀出結(jié)構(gòu)、LSDL電路、脈沖和門控時鐘等高速低功耗設(shè)計技術(shù)。本文對動態(tài)初級譯碼的可靠性、動態(tài)譯碼電路和動態(tài)預(yù)充的讀出結(jié)構(gòu)存在的漏電流進行了分析與優(yōu)化，保證了SRAM可以在較低的頻率（20MHz）下正常工作。實現(xiàn)結(jié)果表明，與Memory Compiler生成的同規(guī)格SRAM相比，全定制設(shè)計的SRAM，面積減小了7.67%，延時減少了35.33%，功耗降低了39.66%。 本文設(shè)計的存儲體，達到了兩款DSP芯片對嵌入式SRAM的性能要求，并為進一步研究雙端口8管或者帶有異步復(fù)位端的高速低功耗SRAM奠定了基礎(chǔ)。
[Abstract]:As the most important semiconductor memory, static random access memory (SRAM) is widely embedded in high performance microprocessors. With the development of IC manufacturing technology, memory occupies more and more power consumption, and high-speed and low-power SRAM design becomes more and more important. In this paper, the design, implementation and verification technology of high-speed and low-power SRAM are studied based on the semi-custom design flow, which is based on standard cell design and realized by manual layout and routing. The main contents are as follows: (1) the design and implementation of high-speed SRAM in 65nm process is based on 13-tube 1W/1R memory cell with asynchronous reset end, which has high read stability and low leakage current. However, it has a large write delay and large layout area. In order to make up for these defects, aiming at the write structure of two-bit line, this paper proposes a low-power bit-line sharing strategy for bit-line sharing. The read decoding and data readout paths achieve faster readout speed at the expense of area and power consumption, which reduces the output delay of the implemented SRAM by 41.62% compared with the SRAM of the same capacity generated by the MemoryCompiler. In the way of realization, the peripheral circuit of SRAM is designed by standard cell and realized by manual layout and routing, which shortens the design period. In this paper, the automatic verification flow of circuit and layout with high simulation precision is developed by script language. (2) the design and implementation of high-speed and low-power SRAM in 40nm process SRAM is based on 10-transistor 1W/2R memory cell, two-stage dynamic decoding, hierarchical dynamic precharge readout structure and LSDL circuit are adopted. High-speed and low-power design techniques such as pulse and gated clock. In this paper, the reliability of the dynamic primary decoding, the leakage current existing in the dynamic decoding circuit and the readout structure of the dynamic precharge are analyzed and optimized, so that the SRAM can work normally at a lower frequency (20MHz). The results show that the SRAM, area, delay and power consumption of the full-custom design are reduced by 7.67%, 35.33% and 39.66%, respectively, compared with the standard SRAM generated by Memory Compiler. The memory bank designed in this paper meets the performance requirements of two DSP chips for embedded SRAM, and lays a foundation for further research on dual-port 8-tube or high-speed and low-power SRAM with asynchronous reset.
【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TP333

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