DDR3控制器的設(shè)計(jì)與驗(yàn)證
發(fā)布時(shí)間：2019-02-20 08:52
【摘要】：伴隨著摩爾定律，現(xiàn)今各種微處理器內(nèi)部的工作頻率不斷上升，存儲(chǔ)器有限的存取速度和外部接口的控制電路的低性能直接影響了系統(tǒng)性能的提升。DDR3SDRAM作為新一代存儲(chǔ)器，有著工作電壓低，功耗小，速度快和容量大等特點(diǎn)，，但是也存在一些局限性。DDR3SDRAM的各種讀寫操作必須要滿足特定的時(shí)序參數(shù)，才能保證內(nèi)存正常工作。DDR3SDRAM控制器采用簡(jiǎn)單的用戶接口，內(nèi)部實(shí)現(xiàn)各種復(fù)雜的DDR3的讀寫操作要求。 本文在研究了DDR3的工作原理和基本操作的基礎(chǔ)上，設(shè)計(jì)出一款高性能控制器。為了提升DDR3的傳輸速率，采用了輸入請(qǐng)求重排序和利用SDRAM中多個(gè)獨(dú)立Bank進(jìn)行并行操作等關(guān)鍵技術(shù)。輸入請(qǐng)求重排序可以有效的提高頁(yè)命中的概率。多個(gè)獨(dú)立Bank并行執(zhí)行可以有效的掩蓋預(yù)充電的時(shí)間，不同Bank交叉執(zhí)行可以大大降低內(nèi)存訪問(wèn)延遲。DDR3控制器采用自頂向下的設(shè)計(jì)方法劃分為各個(gè)模塊，然后用VerilogHDL完成初始化模塊、用戶接口模塊、控制模塊、排序模塊、寫過(guò)程和讀重新排序模塊的RTL編碼。分析了Altera數(shù)字PHY的基本性能的基礎(chǔ)上，設(shè)計(jì)DDR3控制器與數(shù)字PHY的接口模塊。搭建相應(yīng)的仿真驗(yàn)證平臺(tái)，采用隨機(jī)化測(cè)試激勵(lì)自動(dòng)完成測(cè)試結(jié)果和預(yù)期結(jié)果的的比對(duì)，完成了DDR3控制器的主要功能的仿真驗(yàn)證。為以后DDR3內(nèi)存控制器的設(shè)計(jì)提供了參考。
[Abstract]:With Moore's law, the internal frequency of various microprocessors is increasing, the limited memory access speed and the low performance of the external interface control circuit directly affect the performance of the system. DDR3SDRAM as a new generation of memory, It has the characteristics of low working voltage, low power consumption, high speed and large capacity, but it also has some limitations. All kinds of reading and writing operations of DDR3SDRAM must meet certain timing parameters. The DDR3SDRAM controller adopts simple user interface and realizes various complex DDR3 read and write operation requirements. On the basis of studying the working principle and basic operation of DDR3, a high performance controller is designed in this paper. In order to improve the transmission rate of DDR3, the key technologies such as reordering of input requests and parallel operation of multiple independent Bank in SDRAM are adopted. Input request reordering can effectively increase the probability of page hits. Multiple independent Bank parallel execution can effectively cover up the precharge time, different Bank cross execution can greatly reduce the memory access delay. The DDR3 controller is divided into modules by top-down design method. Then VerilogHDL is used to complete the RTL coding of initialization module, user interface module, control module, sort module, write process and read resort module. On the basis of analyzing the basic performance of Altera digital PHY, the interface module between DDR3 controller and digital PHY is designed. The corresponding simulation verification platform is built and the simulation verification of the main functions of the DDR3 controller is completed by automatically comparing the test results with the expected results by using the randomization test excitation. It provides a reference for the design of DDR3 memory controller in the future.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP333
本文編號(hào)：2427025
[Abstract]:With Moore's law, the internal frequency of various microprocessors is increasing, the limited memory access speed and the low performance of the external interface control circuit directly affect the performance of the system. DDR3SDRAM as a new generation of memory, It has the characteristics of low working voltage, low power consumption, high speed and large capacity, but it also has some limitations. All kinds of reading and writing operations of DDR3SDRAM must meet certain timing parameters. The DDR3SDRAM controller adopts simple user interface and realizes various complex DDR3 read and write operation requirements. On the basis of studying the working principle and basic operation of DDR3, a high performance controller is designed in this paper. In order to improve the transmission rate of DDR3, the key technologies such as reordering of input requests and parallel operation of multiple independent Bank in SDRAM are adopted. Input request reordering can effectively increase the probability of page hits. Multiple independent Bank parallel execution can effectively cover up the precharge time, different Bank cross execution can greatly reduce the memory access delay. The DDR3 controller is divided into modules by top-down design method. Then VerilogHDL is used to complete the RTL coding of initialization module, user interface module, control module, sort module, write process and read resort module. On the basis of analyzing the basic performance of Altera digital PHY, the interface module between DDR3 controller and digital PHY is designed. The corresponding simulation verification platform is built and the simulation verification of the main functions of the DDR3 controller is completed by automatically comparing the test results with the expected results by using the randomization test excitation. It provides a reference for the design of DDR3 memory controller in the future.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP333
【參考文獻(xiàn)】
相關(guān)期刊論文 前3條
1 須文波;胡丹;;DDR2 SDRAM控制器的FPGA實(shí)現(xiàn)[J];江南大學(xué)學(xué)報(bào);2006年02期
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3 趙天云,王洪迅,郭雷,畢篤彥;DDR2 SDRAM控制器的設(shè)計(jì)與實(shí)現(xiàn)[J];微電子學(xué)與計(jì)算機(jī);2005年03期
本文編號(hào)：2427025
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