【摘要】：高速緩沖存儲(chǔ)器(Cache)作為微處理器的重要組成部分,在芯片面積和功耗上都占比過高。針對(duì)Cache功耗問題,基于分段訪問Cache技術(shù)和路預(yù)測(cè)Cache技術(shù),提出一種低功耗組相聯(lián)Cache的預(yù)訪問策略。在Cache中增加一個(gè)緩沖寄存器(Buffer),用以存儲(chǔ)最近Cache命中后被訪問的標(biāo)簽和數(shù)據(jù)子陣列信息。在開始進(jìn)行標(biāo)簽訪問之前,選中該Buffer,并將所訪問的Cache標(biāo)簽和Buffer標(biāo)簽進(jìn)行匹配,根據(jù)匹配結(jié)果選擇采用路預(yù)測(cè)訪問或分段訪問方式。通過Mi Bench基準(zhǔn)測(cè)試程序并使用Simple Scalar和Sim-Panalyzer進(jìn)行實(shí)驗(yàn),結(jié)果表明,與傳統(tǒng)組相聯(lián)Cache技術(shù)相比,該策略能降低25.15%的能量延遲積。
[Abstract]:Cache memory (Cache), as an important part of microprocessor, occupies a high proportion of chip area and power consumption. In order to solve the problem of Cache power consumption, a low power group associated Cache pre-access strategy is proposed based on piecewise access Cache technology and path prediction Cache technology. Add a buffer register (Buffer), to Cache to store tags and data subarray information accessed after the most recent Cache hit. Before the tag access is started, the Buffer, is selected and the visited Cache tag and the Buffer tag are matched. According to the matching results, the path prediction access or segmented access is adopted. By using Mi Bench benchmark program and using Simple Scalar and Sim-Panalyzer, the results show that compared with the conventional group associated Cache technique, this strategy can reduce the energy delay product by 25.15%.
【作者單位】： 中國(guó)電子集團(tuán)公司第三十二研究所;
【分類號(hào)】：TP332

【參考文獻(xiàn)】

相關(guān)期刊論文 前2條

1 王冶;張盛兵;王黨輝;;基于預(yù)緩沖機(jī)制的低功耗指令Cache[J];計(jì)算機(jī)工程;2012年01期

2 任小西;劉清;;一種低功耗動(dòng)態(tài)可重構(gòu)cache算法的研究[J];計(jì)算機(jī)應(yīng)用研究;2013年02期

【共引文獻(xiàn)】

相關(guān)期刊論文 前3條

1 張丹;董雷剛;劉雅U，

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