【摘要】：隨著信息技術(shù)的發(fā)展，作為傳統(tǒng)實驗教學(xué)的一種有效補充，虛擬實驗教學(xué)顯現(xiàn)出其直觀，便利的優(yōu)勢。其中用于計算機體系結(jié)構(gòu)與組成原理教學(xué)的CPU模擬器就是虛擬實驗的一個應(yīng)用實例，真實的處理器內(nèi)部結(jié)構(gòu)對外界是不可見的，而傳統(tǒng)教學(xué)模式僅僅通過文字描述和概念講解的方式對特定處理器結(jié)構(gòu)進行介紹，很難使學(xué)生對處理器結(jié)構(gòu)產(chǎn)生整體的理解。模擬器給學(xué)生提供了一個了解計算機內(nèi)部操作的入口，將一個處理器內(nèi)部的操作表面化，并在這上面執(zhí)行程序，觀察指令執(zhí)行過程，來理解真實的機器。 本畢業(yè)設(shè)計以深入理解計算機系統(tǒng)一書為基礎(chǔ)，在分析IA32指令集簡單子集“Y86”的基礎(chǔ)上，實現(xiàn)了功能層次的Y86指令集模擬器YIS，以便與其他版本模擬器運行結(jié)果相比較，檢測其設(shè)計運行的正確性。在功能模擬的基礎(chǔ)上，通過對順序及流水線技術(shù)的理解，設(shè)計完成三個版本的周期精度性能模擬器。本文遵循“從簡單到復(fù)雜的循序漸進的”基本思路，論述了這三個版本的硬件模型：順序Y86處理器模擬器ssim及其重排擴展ssim+，流水線化Y86處理器模擬器psim。此外，完成了配套的指令匯編器，方便學(xué)生輸入?yún)R編語言生成二進制文件。以上所有工具運行在windows操作系統(tǒng)上，具有終端與用戶圖形接口兩種模式，用于觀察Y86指令執(zhí)行過程中處理階段信號、寄存器內(nèi)容、條件碼等狀態(tài)信息，，從而作為教學(xué)實驗平臺。
[Abstract]:With the development of information technology, as an effective supplement to the traditional experimental teaching, virtual experimental teaching shows its intuitive and convenient advantages. The CPU simulator used in the teaching of computer architecture and composition principle is an application example of virtual experiment, and the real internal structure of the processor is invisible to the outside world. However, the traditional teaching mode only introduces the specific processor architecture by the way of word description and concept explanation, so it is very difficult for the students to have an overall understanding of the processor architecture. The simulator provides a way for students to understand the internal operation of a computer, to surface the operation inside a processor, and to execute the program on it and observe the execution process of the instruction to understand the real machine. This graduation design is based on a deep understanding of computer systems. On the basis of analyzing the simple subset of IA32 instruction set "Y86", the functional level Y86 instruction set simulator YIS, is implemented in order to compare the running results with other versions of simulator. Check the correctness of its design and operation. Based on the functional simulation and the understanding of sequence and pipeline technology, three versions of the cycle accuracy performance simulator are designed. This paper follows the basic idea of "from simple to complex step by step", and discusses the three versions of the hardware model: sequential Y86 processor simulator ssim and its rearrangement extended ssim, pipeline Y86 processor simulator psim. In addition, a complete set of instruction assembler is completed, which is convenient for students to input assembly language to generate binary files. All of the above tools run on the windows operating system and have two modes of interface between terminal and user. They are used to observe the state information of processing phase signal, register content, condition code and so on during the execution of Y86 instruction, so as to serve as the teaching experiment platform.
【學(xué)位授予單位】：中國地質(zhì)大學(xué)（北京）
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TP332

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