基于OpenRISC1200 32位CPU的miniSoC系統(tǒng)設(shè)計和軟硬件驗證
發(fā)布時間：2018-12-20 06:01
【摘要】：在整個廣泛的集成電路產(chǎn)業(yè)中，幾乎每一個SoC內(nèi)部都集成和應(yīng)用了一款CPU。由于CPU設(shè)計技術(shù)的復(fù)雜性和高度保密性，商業(yè)化處理器及其IP核價格昂貴，同時，很少有公開的資料對內(nèi)部邏輯實現(xiàn)進行詳細介紹，若作為積累CPU設(shè)計經(jīng)驗、降低設(shè)計成本和技術(shù)門檻的研究對象不太適合。如果選擇開源的CPU系列，會有較為完整的資料，這樣的CPU目前也有不少，比如OpenRISC和LEON等，這里我們選擇OpenRISC OR1200作為我們研究的對象。 OR1200是開放源代碼處理器，為OpenCores組織基于GPL協(xié)議提供，其性能可以為一般的嵌入式系統(tǒng)使用。同時OpenCores組織和部分開源愛好者提供了比較完整的開放源代碼IP核、開發(fā)資料供研究人員使用[40]。 本論文先介紹計算機體系結(jié)構(gòu)的基礎(chǔ)內(nèi)容，闡述計算機體系結(jié)構(gòu)對嵌入式處理器設(shè)計和測試的重要性，主要為硬件和軟件功能的劃分，確定硬件和軟件的分界。了解嵌入式處理器設(shè)計應(yīng)考慮成本、價格和發(fā)展趨勢，性能評估及基準測試程序。有助于軟件程序設(shè)計人員編寫出高質(zhì)量程序，處理器設(shè)計人員能提供軟件開發(fā)更好的設(shè)計架構(gòu)確保其正常高效運行。 本論文研究了OpenRISC的地址與尋址方式、指令集和指令格式，流水線等內(nèi)容，詳細研究了OR1200核心、Cache、MMU、DEBUG等組成的處理器最核心架構(gòu)，各設(shè)計單元功能之間的數(shù)據(jù)交互和處理方式，，掌握典型處理器獨立工作、軟件調(diào)試等整體系統(tǒng)的設(shè)計能力。 本論文對Wishbone總線協(xié)議及互連類型詳細分析。Wishbone總線規(guī)范也是一種片上系統(tǒng)IP核互連體系結(jié)構(gòu)，需要集成的IP核遵照總線規(guī)范協(xié)議，提供相同的公共邏輯接口，在大規(guī)模集成方面易于實施，易于重用，易于移植，同時驗證和可靠性都得到了提高[1]。 在分析完處理器架構(gòu)后，設(shè)計miniSoC系統(tǒng)，并下載到FPGA硬件平臺，基于Cygwin環(huán)境下進行軟件開發(fā)環(huán)境和軟件工具的移植和測試，實現(xiàn)了miniSoC系統(tǒng)的軟硬件驗證，此系統(tǒng)便于后續(xù)集成更多IP、并協(xié)同軟件共同開發(fā)。
[Abstract]:Almost every SoC has integrated and applied a CPU. in the whole integrated circuit industry Because of the complexity and high confidentiality of CPU design technology, the commercial processor and its IP core are expensive. At the same time, there are few open data to introduce the implementation of internal logic in detail, if as a result of accumulating CPU design experience, The research object that reduces the design cost and the technical threshold is not suitable. If you choose the open source CPU series, there will be more complete information, such as the current CPU, such as OpenRISC and LEON, and so on, here we choose OpenRISC OR1200 as our research object. OR1200 is an open source processor for OpenCores organization based on GPL protocol, its performance can be used for general embedded systems. At the same time, the OpenCores organization and some open source enthusiasts provide a relatively complete open source IP core, development materials for researchers to use [40]. This paper first introduces the basic contents of computer architecture, expounds the importance of computer architecture for embedded processor design and testing, mainly for the division of hardware and software functions, and determines the distinction between hardware and software. Understand embedded processor design should consider cost, price and development trends, performance evaluation and benchmarking procedures. It is helpful for software programmers to write high quality programs, and processor designers can provide better design architecture for software development to ensure its normal and efficient operation. This paper studies the address and addressing mode of OpenRISC, instruction set and instruction format, pipeline and so on, and studies the core architecture of OR1200, Cache,MMU,DEBUG and so on in detail. The data exchange and processing between the functions of each design unit, master the design ability of the system such as the typical processor working independently, software debugging and so on. In this paper, the Wishbone bus protocol and the interconnection type are analyzed in detail. The Wishbone bus specification is also a kind of on-chip system IP core interconnection architecture. The IP core that needs to be integrated provides the same common logic interface according to the bus specification protocol. Large scale integration is easy to implement, easy to reuse, easy to transplant, at the same time, verification and reliability have been improved [1]. After analyzing the processor architecture, the miniSoC system is designed and downloaded to the FPGA hardware platform. The software development environment and software tools are transplanted and tested based on the Cygwin environment, and the software and hardware verification of the miniSoC system is realized. This system is convenient to integrate more IP, and develop together with software.
【學位授予單位】：電子科技大學
【學位級別】：碩士
【學位授予年份】：2013
【分類號】：TP332
本文編號：2387536
[Abstract]:Almost every SoC has integrated and applied a CPU. in the whole integrated circuit industry Because of the complexity and high confidentiality of CPU design technology, the commercial processor and its IP core are expensive. At the same time, there are few open data to introduce the implementation of internal logic in detail, if as a result of accumulating CPU design experience, The research object that reduces the design cost and the technical threshold is not suitable. If you choose the open source CPU series, there will be more complete information, such as the current CPU, such as OpenRISC and LEON, and so on, here we choose OpenRISC OR1200 as our research object. OR1200 is an open source processor for OpenCores organization based on GPL protocol, its performance can be used for general embedded systems. At the same time, the OpenCores organization and some open source enthusiasts provide a relatively complete open source IP core, development materials for researchers to use [40]. This paper first introduces the basic contents of computer architecture, expounds the importance of computer architecture for embedded processor design and testing, mainly for the division of hardware and software functions, and determines the distinction between hardware and software. Understand embedded processor design should consider cost, price and development trends, performance evaluation and benchmarking procedures. It is helpful for software programmers to write high quality programs, and processor designers can provide better design architecture for software development to ensure its normal and efficient operation. This paper studies the address and addressing mode of OpenRISC, instruction set and instruction format, pipeline and so on, and studies the core architecture of OR1200, Cache,MMU,DEBUG and so on in detail. The data exchange and processing between the functions of each design unit, master the design ability of the system such as the typical processor working independently, software debugging and so on. In this paper, the Wishbone bus protocol and the interconnection type are analyzed in detail. The Wishbone bus specification is also a kind of on-chip system IP core interconnection architecture. The IP core that needs to be integrated provides the same common logic interface according to the bus specification protocol. Large scale integration is easy to implement, easy to reuse, easy to transplant, at the same time, verification and reliability have been improved [1]. After analyzing the processor architecture, the miniSoC system is designed and downloaded to the FPGA hardware platform. The software development environment and software tools are transplanted and tested based on the Cygwin environment, and the software and hardware verification of the miniSoC system is realized. This system is convenient to integrate more IP, and develop together with software.
【學位授予單位】：電子科技大學
【學位級別】：碩士
【學位授予年份】：2013
【分類號】：TP332
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