【摘要】：多核時代微處理器設(shè)計面臨的功耗、訪存、互連等問題進(jìn)一步惡化。三維集成電路（3D IC）是一種新的集成電路工藝，通過將多層硅片使用硅通孔（TSV）連接可以增加單芯片封裝內(nèi)的硅片資源、縮短硅片間全局連線，使得芯片內(nèi)部能夠容納更多核心與相關(guān)資源。片上網(wǎng)絡(luò)（NoC）則是一種面向多核與眾核處理器通訊需求的結(jié)構(gòu)化互連設(shè)計方法。3D IC和NoC都是大規(guī)模集成電路設(shè)計發(fā)展重要方向。將兩者結(jié)合的三維片上網(wǎng)絡(luò)（3D NoC）可以同時發(fā)揮3D IC和NoC的互連部件多、帶寬高、延遲低的優(yōu)勢，是當(dāng)前研究的熱點之一。 現(xiàn)有三維片上網(wǎng)絡(luò)拓?fù)浣Y(jié)構(gòu)的研究，都是針對4層左右硅片堆疊無法進(jìn)一步擴展。然而10層以上硅片堆疊的可能性已經(jīng)得到證明。本文利用三維集成電路中硅通孔（TSV）具有延遲短、功耗小的特性，針對10層以上硅片堆疊的三維片上網(wǎng)絡(luò)，設(shè)計了一種新的拓?fù)浣Y(jié)構(gòu)3DE-Mesh。通過實驗數(shù)據(jù)的分析，證明3DE-Mesh在性能和可擴展性方面都適合于10層以上硅片堆疊的三維集成電路。 現(xiàn)有3D NoC的研究，基本上都是采用固定結(jié)構(gòu)的路由器，網(wǎng)絡(luò)性能會隨堆疊層數(shù)增加而下降，同時沒有充分利用3D IC中硅通孔（TSV）延遲短、功耗小的特性。為了充分發(fā)掘TSV的特性，并面向未來多層TSV堆疊擴展需求，，本文提出了一種硅片間擴展路由器（EIDR），并設(shè)計了使用該路由器構(gòu)建的硅片間單跳步（SHID）體系結(jié)構(gòu)。SHID能通過增加TSV數(shù)量獲得性能改善。實驗數(shù)據(jù)的分析表明，與3D-Mesh和NoC-Bus這兩種已有的3D NoC結(jié)構(gòu)相比SHID結(jié)構(gòu)有以下特點：1）SHID體系結(jié)構(gòu)的延遲較低，4層堆疊時比3D-Mesh低15.1%，比NoC-Bus低11.5%；2）SHID體系結(jié)構(gòu)的功耗與NoC-Bus相當(dāng)，比3D-Mesh低10%左右；3）SHID體系結(jié)構(gòu)的吞吐率隨堆疊層數(shù)增加下降緩慢，16層堆疊時吞吐率比3D-Mesh高66.98%，比Noc-Bus高314.49%。 多層堆疊的三維拓?fù)浣Y(jié)構(gòu)3DE-Mesh與SHID體系結(jié)構(gòu)彌補了現(xiàn)有三維NOC結(jié)構(gòu)研究中擴展能力不足的缺點，同時具備性能和可擴展性的優(yōu)勢，是未來3DNoC體系結(jié)構(gòu)良好設(shè)計選擇。
[Abstract]:The power consumption, memory access, interconnection and other problems of microprocessor design in multi-core era are getting worse. Three-dimensional integrated circuit (3D IC) is a new integrated circuit technology. By connecting multilayer silicon wafer with silicon through hole (TSV), we can increase the silicon chip resource in single chip package and shorten the global connection between silicon wafers. So that the chip can accommodate more core and related resources. On-chip network (NoC) is a kind of structured interconnect design method to meet the communication requirements of multi-core and multi-core processors. 3D IC and NoC are both important directions in the development of VLSI design. The combination of 3D NoC and 3D IC can bring into play the advantages of many interconnecting parts, high bandwidth and low delay of 3D IC and NoC, so it is one of the hot research topics at present. The existing research of three-dimensional on-chip network topology is aimed at the 4-layer stack of silicon wafers which can not be further expanded. However, the possibility of stacking more than 10 layers of silicon wafers has been proved. In this paper, a new topology 3DE-Mesh. is designed for the three dimensional on-chip network with more than 10 layers of silicon wafers, which has the characteristics of short delay and low power consumption of silicon through hole (TSV) in 3D integrated circuits. Through the analysis of experimental data, it is proved that 3DE-Mesh is suitable for three dimensional integrated circuits with more than 10 layers of silicon chips in terms of performance and extensibility. The existing researches on 3D NoC are based on fixed structure routers, and the network performance will decrease with the increase of stacking layers. At the same time, it does not make full use of the characteristics of short (TSV) delay and low power consumption in 3D IC. In order to fully explore the characteristics of TSV and to meet the needs of multilayer TSV stack expansion in the future, this paper proposes a kind of (EIDR), for interwafer expansion router. A single step (SHID) architecture with this router is designed. SHID can be improved by increasing the number of TSV acquired. The analysis of experimental data shows that compared with 3D-Mesh and NoC-Bus, the SHID structure has the following characteristics: 1) the delay of SHID architecture is lower, 15.1 layers lower than 3D-Mesh and 11.5% lower than NoC-Bus; 2) the power consumption of SHID architecture is about the same as that of NoC-Bus, which is about 10% lower than that of 3D-Mesh; 3) the throughput of the SHID architecture decreases slowly with the increase of the number of stacked layers. The throughput of 16 layers is 66.98 higher than that of 3D-Mesh and 314.49 higher than that of Noc-Bus. Multi-layer stacked 3D topology 3DE-Mesh and SHID architecture make up for the shortcomings of the existing 3D NOC architecture in the research of the lack of extensibility. At the same time, it has the advantages of performance and scalability. It is a good design choice for the future 3DNoC architecture.
【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2012
【分類號】：TP332

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