發(fā)布時(shí)間：2018-12-09 10:35

【摘要】：浮點(diǎn)運(yùn)算在各種工程計(jì)算和科學(xué)計(jì)算中的應(yīng)用非常廣泛。在一些對(duì)速度要求較高的情況下,必須采用一個(gè)專門的浮點(diǎn)運(yùn)算器。 到目前為止,由于現(xiàn)場(chǎng)可編程門陣列(FPGA)發(fā)展迅速,應(yīng)用EDA技術(shù),設(shè)計(jì)浮點(diǎn)運(yùn)算,已成為研究熱點(diǎn),所以本文是基于FPGA來研究浮點(diǎn)運(yùn)算的。主要研究了IEEE754標(biāo)準(zhǔn)的浮點(diǎn)數(shù)的表示及加減、乘、除運(yùn)算規(guī)則,結(jié)合已有的浮點(diǎn)運(yùn)算硬件模型,分析了用Verilog HDL語(yǔ)言程序?qū)崿F(xiàn)的64位浮點(diǎn)數(shù)的加減、乘、除基本的運(yùn)算功能的實(shí)現(xiàn)方法,并在QuartusⅡ環(huán)境下,將程序進(jìn)行編譯、綜合、調(diào)試,做出功能和時(shí)序仿真；同時(shí)用C語(yǔ)言編寫程序,用來實(shí)現(xiàn)將兩個(gè)雙精度浮點(diǎn)數(shù)進(jìn)行加減、乘、除,并將結(jié)果轉(zhuǎn)換成符合IEEE754標(biāo)準(zhǔn)的雙精度浮點(diǎn)數(shù)的二進(jìn)制形式輸出,其目的是用這個(gè)結(jié)果來驗(yàn)證仿真結(jié)果,如果結(jié)果一致,說明Verilog HDL語(yǔ)言程序正確。由于條件有限,無法將64位浮點(diǎn)運(yùn)算的程序直接下載到現(xiàn)有FPGA上,所以最后以浮點(diǎn)加減法為例,將浮點(diǎn)位數(shù)縮短成7位,修改程序,再進(jìn)行仿真、下載與配置。
[Abstract]:Floating-point operations are widely used in various engineering and scientific calculations. A special floating-point operator must be used in some cases with high speed requirements. So far, due to the rapid development of field programmable gate array (FPGA), the application of EDA technology to design floating-point operations has become a research hotspot. Therefore, this paper is based on FPGA to study floating-point operations. This paper mainly studies the representation, addition and subtraction, multiplication and division rules of IEEE754 standard floating-point number, combining with the existing floating-point operation hardware model, analyzes the addition and subtraction and multiplication of 64-bit floating-point number realized by Verilog HDL program. In addition to the basic operation function realization method, and under the Quartus 鈪，

本文編號(hào)：2369240