一種應用于指令級并行處理器的低功耗并行度調(diào)整方案(英文)
發(fā)布時間:2018-12-06 10:53
【摘要】:對于指令級并行處理器(ILP,instruction level parallelism),在執(zhí)行不同應用程式時,硬件資源的需求量差異很大,甚至在同一支程式中也是如此,某些空閑的硬件資源會產(chǎn)生額外的靜態(tài)能量,提出重新設置應用程式中不同區(qū)塊的執(zhí)行并行度,把空閑的硬件資源關(guān)斷來降低靜態(tài)能量的方案,利用Core Mark Pro的標準測試集中的應用程式進行測試,靜態(tài)能量降低超過40%且執(zhí)行時間增加少于10%.
[Abstract]:For instruction-level parallel processors (ILP,instruction level parallelism), requires a lot of hardware resources when running different applications, even in the same program, some idle hardware resources generate additional static energy. This paper proposes a scheme to reset the execution parallelism of different blocks in the application, turn off the idle hardware resources to reduce the static energy, and use the application program in the standard test set of Core Mark Pro to test. The static energy is reduced by more than 40% and the execution time is increased by less than 10%.
【作者單位】: 天津大學電子信息工程學院;長庚大學資訊工程系;
【分類號】:TP332
本文編號:2365922
[Abstract]:For instruction-level parallel processors (ILP,instruction level parallelism), requires a lot of hardware resources when running different applications, even in the same program, some idle hardware resources generate additional static energy. This paper proposes a scheme to reset the execution parallelism of different blocks in the application, turn off the idle hardware resources to reduce the static energy, and use the application program in the standard test set of Core Mark Pro to test. The static energy is reduced by more than 40% and the execution time is increased by less than 10%.
【作者單位】: 天津大學電子信息工程學院;長庚大學資訊工程系;
【分類號】:TP332
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