XDNP網絡處理器快速總線接口FBI設計與實現
發(fā)布時間：2018-12-05 19:57
【摘要】：隨著互聯網技術的快速發(fā)展，網絡處理器作為現代網絡系統(tǒng)的核心設備，正在向著多核片上系統(tǒng)的方向發(fā)展；隨著微電子技術的迅猛發(fā)展，如今已進入了超深亞微米、納米時代，，為了滿足性能、功耗和成本的需求，芯片的物理實現也越來越復雜。 作為網絡處理器的數據交換樞紐，快速總線接口FBI承載了網絡端口和包處理引擎以及SDRAM單元之間眾多的數據通路和控制通路，它是實現網絡處理器與外部數據交換的平臺，因此快速總線接口FBI是決定網絡處理器性能的關鍵單元之一。如何設計并實現快速總線接口FBI對于高性能網絡處理器系統(tǒng)顯得至關重要。 本文首先重點描述了在快端口模式中XDNP網絡處理器的工作機制，規(guī)范了快速總線接口FBI的功能和體系框架：生成微包的序列號，協(xié)助包處理引擎PE保持數據分組的順序；使用了雙口結構的SRAM作為數據緩存單元，解決了異步時鐘域之間的數據同步化問題；采用了DMA的方式，減輕了包處理引擎PE的工作負擔；設計了PUSH/PULL引擎的命令隊列，對來自于包處理引擎PE與SDRAM控制器的指令代碼進行仲裁與排隊操作，這樣解決了包處理引擎PE可能同時有多個線程向快速總線接口FBI發(fā)出轉發(fā)數據包指令的問題。 接著本文完成了快速總線接口FBI的詳細設計方案，分別介紹了PUSH/PULL引擎、接收/發(fā)送控制器、接收/發(fā)送緩存的設計，并從綜合約束、設計優(yōu)化等方面給出了快速總線接口FBI的具體實現和優(yōu)化，詳細分析了時序違例和優(yōu)化的方法。在最壞條件下快速總線接口FBI的最高工作頻率達到233MHz，優(yōu)于系統(tǒng)設計目標頻率要求。最后根據綜合得到的網表和約束文件在SMICCMOS130nm工藝下完成了快速總線接口FBI的物理實現工作。
[Abstract]:With the rapid development of Internet technology, network processor, as the core equipment of modern network system, is developing towards the direction of multi-core on-chip system. With the rapid development of microelectronics technology, the physical realization of chips is becoming more and more complicated in order to meet the demand of performance, power consumption and cost. As the data exchange hub of the network processor, the fast bus interface (FBI) carries many data paths and control paths between the network port, packet processing engine and SDRAM unit. It is the platform to realize the data exchange between the network processor and the external data. So the fast bus interface (FBI) is one of the key units to determine the performance of the network processor. How to design and implement fast bus interface (FBI) is very important for high performance network processor system. In this paper, the working mechanism of XDNP network processor in fast port mode is described, and the function and architecture of fast bus interface (FBI) are standardized. The sequence number of micropacket is generated to help the packet processing engine (PE) keep the order of data packet. The dual-port structure of SRAM is used as the data buffer unit to solve the problem of data synchronization between asynchronous clock domains, and the way of DMA is adopted to reduce the workload of packet processing engine PE. The command queue of PUSH/PULL engine is designed to arbitrate and queue the instruction code from packet processing engine PE and SDRAM controller. This solves the problem that the packet processing engine PE may have multiple threads simultaneously sending forward packet instructions to the fast bus interface FBI. Then, this paper completes the detailed design of FBI, introduces the design of PUSH/PULL engine, receiver / transmitter controller, receive / transmit cache, and synthesizes constraints. The realization and optimization of fast bus interface FBI are given, and the methods of timing violation and optimization are analyzed in detail. In the worst case, the maximum operating frequency of the fast bus interface FBI is 233MHz, which is better than the target frequency requirement of the system design. Finally, the physical implementation of the fast bus interface (FBI) under the SMICCMOS130nm process is completed according to the network table and constraint file.
【學位授予單位】：西安電子科技大學
【學位級別】：碩士
【學位授予年份】：2013
【分類號】：TP334.7;TN432
本文編號：2365391
[Abstract]:With the rapid development of Internet technology, network processor, as the core equipment of modern network system, is developing towards the direction of multi-core on-chip system. With the rapid development of microelectronics technology, the physical realization of chips is becoming more and more complicated in order to meet the demand of performance, power consumption and cost. As the data exchange hub of the network processor, the fast bus interface (FBI) carries many data paths and control paths between the network port, packet processing engine and SDRAM unit. It is the platform to realize the data exchange between the network processor and the external data. So the fast bus interface (FBI) is one of the key units to determine the performance of the network processor. How to design and implement fast bus interface (FBI) is very important for high performance network processor system. In this paper, the working mechanism of XDNP network processor in fast port mode is described, and the function and architecture of fast bus interface (FBI) are standardized. The sequence number of micropacket is generated to help the packet processing engine (PE) keep the order of data packet. The dual-port structure of SRAM is used as the data buffer unit to solve the problem of data synchronization between asynchronous clock domains, and the way of DMA is adopted to reduce the workload of packet processing engine PE. The command queue of PUSH/PULL engine is designed to arbitrate and queue the instruction code from packet processing engine PE and SDRAM controller. This solves the problem that the packet processing engine PE may have multiple threads simultaneously sending forward packet instructions to the fast bus interface FBI. Then, this paper completes the detailed design of FBI, introduces the design of PUSH/PULL engine, receiver / transmitter controller, receive / transmit cache, and synthesizes constraints. The realization and optimization of fast bus interface FBI are given, and the methods of timing violation and optimization are analyzed in detail. In the worst case, the maximum operating frequency of the fast bus interface FBI is 233MHz, which is better than the target frequency requirement of the system design. Finally, the physical implementation of the fast bus interface (FBI) under the SMICCMOS130nm process is completed according to the network table and constraint file.
【學位授予單位】：西安電子科技大學
【學位級別】：碩士
【學位授予年份】：2013
【分類號】：TP334.7;TN432
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