【摘要】：近年來(lái),隨著科學(xué)技術(shù)的發(fā)展,以及人們對(duì)計(jì)算機(jī)更高的性能要求,采用商用器件來(lái)構(gòu)建航天設(shè)備已經(jīng)成為了國(guó)內(nèi)外的發(fā)展趨勢(shì)。相比于傳統(tǒng)的航空航天級(jí)的芯片器件,商用器件具有性能超群、成本低廉、數(shù)量充裕等優(yōu)勢(shì),能夠滿足航空航天設(shè)備日益增長(zhǎng)的性能需求。但惡劣的太空環(huán)境會(huì)給星載計(jì)算機(jī)的可靠性帶來(lái)十分嚴(yán)峻的問(wèn)題,商用器件的缺陷在于抗輻照能力低,在惡劣的太空環(huán)境下,商用器件受高能粒子輻照極易發(fā)生故障。而軟件容錯(cuò)技術(shù)讓我們?cè)诓焕每馆椪諏Ｓ眯酒臈l件下也可以取得可靠性保證。但是,軟件容錯(cuò)技術(shù)的大量復(fù)算工作會(huì)大大提高系統(tǒng)的能量開(kāi)銷,如何削減能耗成為一個(gè)必須解決的問(wèn)題。本文在研究了控制流和數(shù)據(jù)流軟件容錯(cuò)算法的基礎(chǔ)上,針對(duì)高性能的商用DSP-TMS320C6748硬件實(shí)驗(yàn)平臺(tái),提出了軟加固高性能處理器的功耗優(yōu)化方法。本文的主要工作和創(chuàng)新有以下幾點(diǎn):(1)深入研究了軟件容錯(cuò)技術(shù)的數(shù)據(jù)流和控制流容錯(cuò)算法以及功耗優(yōu)化技術(shù),總結(jié)了DSP硬件平臺(tái)的特點(diǎn),設(shè)計(jì)了從軟加固前至軟加固算法再至軟加固后的三階段、全方位的針對(duì)軟件容錯(cuò)進(jìn)行性能和功耗優(yōu)化的優(yōu)化流程。(2)分析應(yīng)用了基于C/C++語(yǔ)言和基于匯編語(yǔ)言的低功耗優(yōu)化方法。面向C/C++語(yǔ)言,針對(duì)循環(huán)代碼,總結(jié)了包括循環(huán)展開(kāi)、循環(huán)合并、循環(huán)分塊等低功耗優(yōu)化方法。在匯編語(yǔ)言下,針對(duì)C6000系列DSP獨(dú)特的線性匯編,總結(jié)了內(nèi)聯(lián)、嵌入等低功耗優(yōu)化方法。通過(guò)實(shí)驗(yàn)驗(yàn)證,在進(jìn)行軟件容錯(cuò)處理之前,使用以上方法進(jìn)行優(yōu)化,平均性能提升幅度為36.2%。(3)分析軟加固算法的特點(diǎn)及流程,結(jié)合DSP的流水特點(diǎn),面向DSP硬件平臺(tái),對(duì)軟加固算法進(jìn)行改進(jìn),提出了基于DSP線性匯編的循環(huán)優(yōu)化算法SFLOA,以增加容錯(cuò)延遲為代價(jià),在不降低錯(cuò)誤檢測(cè)率的同時(shí),能更充分利用DSP的流水線,大幅降低程序運(yùn)行周期數(shù),降低系統(tǒng)總能量消耗。通過(guò)實(shí)驗(yàn)驗(yàn)證,在容錯(cuò)過(guò)程中,使用SFLOA算法對(duì)容錯(cuò)算法的改進(jìn),可以使平均功耗優(yōu)化幅度達(dá)到79.995%,平均性能提升幅度為57.76%。(4)在軟加固處理之后的優(yōu)化階段中,提出了基于軟加固循環(huán)的動(dòng)態(tài)電壓調(diào)度算法LFDVS。該算法以容錯(cuò)后的循環(huán)為基本單位,對(duì)每個(gè)循環(huán)分配不同的處理器頻率,結(jié)合對(duì)復(fù)雜循環(huán)的靜態(tài)調(diào)度和對(duì)簡(jiǎn)單循環(huán)的動(dòng)態(tài)調(diào)度,在保證檢錯(cuò)率的前提下,能最大化利用CPU的空閑時(shí)間來(lái)進(jìn)行降低電壓和頻率。通過(guò)實(shí)驗(yàn)數(shù)據(jù)可以看出該算法能顯著地降低能量開(kāi)銷。
[Abstract]:In recent years, with the development of science and technology, as well as the higher performance requirements of computers, the use of commercial devices to build aerospace equipment has become a trend of development at home and abroad. Compared with the conventional chip devices, commercial devices have the advantages of superior performance, low cost and abundant quantity, which can meet the increasing performance requirements of aerospace equipment. However, the bad space environment will bring serious problems to the reliability of spaceborne computer. The defect of commercial devices lies in their low radiation resistance. In the harsh space environment, commercial devices are prone to failure when irradiated by high-energy particles. Software fault-tolerant technology allows us to obtain reliability guarantees without the use of radiation-resistant dedicated chips. However, a large amount of software fault-tolerant technology will greatly increase the energy cost of the system, how to reduce energy consumption has become a problem that must be solved. Based on the research of fault-tolerant algorithms for control flow and data flow software, this paper presents a power optimization method for high performance DSP-TMS320C6748 processors based on high performance commercial DSP-TMS320C6748 hardware experimental platform. The main work and innovations of this paper are as follows: (1) the fault-tolerant algorithms of data flow and control flow and the power optimization technology of software fault-tolerant technology are deeply studied, and the characteristics of DSP hardware platform are summarized. The three stages from the soft reinforcement to the soft reinforcement algorithm and to the soft reinforcement algorithm are designed. The software fault-tolerant performance and power optimization process is all-around. (2) A low power optimization method based on C / C language and assembly language is applied. For C / C language, low power optimization methods including loop expansion, loop merging and loop block are summarized for cyclic code. Based on the unique linear assembly of C6000 series DSP, low power optimization methods such as inline and embedding are summarized in assembly language. The experimental results show that before the software fault-tolerant processing, the above methods are used to optimize, and the average performance improvement range is 36.2. (3) the characteristics and flow of the soft reinforcement algorithm are analyzed, combined with the flow characteristics of DSP. For the hardware platform of DSP, the soft reinforcement algorithm is improved, and the cyclic optimization algorithm SFLOA, based on DSP linear assembly is proposed, which can make full use of the pipeline of DSP without reducing the error detection rate at the cost of increasing fault tolerant delay. Greatly reduce the number of program running cycles, reduce the total energy consumption of the system. Experimental results show that in the process of fault tolerance, the improved SFLOA algorithm can improve the average power consumption to 79.9955. The average performance improvement range is 57.76. (4) in the optimization stage after soft reinforcement treatment, a dynamic voltage scheduling algorithm LFDVS. based on soft reinforcement cycle is proposed. The algorithm takes fault-tolerant cycles as the basic unit, assigns different processor frequencies to each cycle, combines the static scheduling of complex cycles and the dynamic scheduling of simple loops, and ensures the error detection rate. Can maximize the use of CPU idle time to reduce the voltage and frequency. The experimental data show that the algorithm can significantly reduce the energy cost.
【學(xué)位授予單位】：國(guó)防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：V446;TP302.7
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本文編號(hào)：2348964