【摘要】：為了解決當(dāng)前橢圓曲線密碼處理器普遍存在靈活性低、資源占用大的問題,該文采用統(tǒng)計(jì)建模的方式,以面積-時(shí)間(AT)綜合性能指標(biāo)為指導(dǎo),提出了一種面向橢圓曲線密碼并行處理架構(gòu)的量化評估方式,并確定3路異構(gòu)并行處理架構(gòu)可使處理器綜合性能達(dá)到最優(yōu)。其次,該文提出一個(gè)分離分級式存儲結(jié)構(gòu)和一個(gè)運(yùn)算資源高度復(fù)用的模運(yùn)算單元,可增強(qiáng)存儲器的訪問效率和運(yùn)算資源的利用率。在90 nm CMOS工藝下綜合,該文處理器的面積為1.62 mm~2,完成一次GF(2~(571))和GF(p~(521))上的點(diǎn)乘運(yùn)算分別需要2.26 ms/612.4μJ和2.63 ms/665.4μJ。與同類設(shè)計(jì)相比,該文處理器不僅具有較高的靈活性、可伸縮性,而且其芯片面積和運(yùn)算速度達(dá)到了很好的折中。
[Abstract]:In ord to solve that problem that the current elliptic curve password processor is low in flexibility and large in resource occupation, a statistical modeling method is adopted to guide the comprehensive performance index of the area-time (AT), In this paper, a quantitative evaluation method for elliptic curve code parallel processing architecture is proposed, and the three-way heterogeneous parallel processing architecture is determined to make the comprehensive performance of the processor optimal. Secondly, this paper proposes a separate hierarchical storage structure and a high-level multiplexing model arithmetic unit, which can enhance the access efficiency of the memory and the utilization rate of the operation resources. In the process of 90 nm CMOS, the area of the processor is 1.62 mm ~ 2, and the point multiplication on GF (2 ~ (571)) and GF (p ~ (521)) needs to be 2.26 ms/ 612.4uJ and 2.63ms/ 664.mu. J respectively. Compared with the same kind of design, the processor not only has high flexibility and scalability, and the chip area and the operation speed of the chip are very good compromise.
【作者單位】： 解放軍信息工程大學(xué);復(fù)旦大學(xué)專用集成電路與系統(tǒng)國家重點(diǎn)實(shí)驗(yàn)室;
【基金】：國家自然科學(xué)基金(61404175)~~
【分類號】：TP332
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本文編號：2342109