高速大容量存儲器的控制器設(shè)計與驗證
發(fā)布時間：2018-11-18 19:58
【摘要】：現(xiàn)如今,處理器技術(shù)的發(fā)展日新月異,其對高速大容量存儲器性能的要求也越發(fā)的嚴苛。而在各類常用的隨機存儲器件中,尤以DDR3存儲器的使用最為廣泛。DDR3存儲器具有速率高、容量大、售價低廉等多種優(yōu)勢。由于存儲器無法對處理器的訪存命令做出直接的應(yīng)答,且操作起來邏輯十分復(fù)雜,對讀寫時序的要求也尤其嚴格,因而設(shè)計出一款效能良好的存儲器控制器將是該領(lǐng)域今后很長一段時間努力的重點。另外,近些年FPGA整體性能的提升也越發(fā)的迅猛。新一代的FPGA已經(jīng)能夠提供更多的邏輯資源、更快的運算速度和更豐富的存儲器接口解決方案。因此,選用FPGA來輔助進行存儲器控制器的設(shè)計受到越來越多開發(fā)人員的青睞。本文以DDR3高速大容量存儲器為研究對象,結(jié)合存儲器的國內(nèi)外發(fā)展現(xiàn)狀,對DDR3存儲芯片的特性及使用原理進行了深入細致地分析。最終,設(shè)計出一款以Altera公司Stratix Ⅳ系列FPGA為開發(fā)平臺的DDR3控制器,完成了與新型UniPHY物理接口的集成。之后搭建了相應(yīng)的測試平臺,通過相關(guān)軟件完成了控制器的仿真測試及FPGA驗證工作。測試的結(jié)果與預(yù)期相符,驗證了控制器設(shè)計的正確性。具體完成的工作如下:(1)從DDR3存儲器的內(nèi)部結(jié)構(gòu)及工作機理出發(fā),對存儲器的讀寫控制時序進行了詳細的分析;(2)系統(tǒng)地規(guī)劃了DDR3控制器的整體架構(gòu),對控制器內(nèi)部每個子系統(tǒng)的功能、設(shè)計思路及實現(xiàn)方式進行了細致的描述;(3)對新型UniPHY物理IP核的內(nèi)部結(jié)構(gòu)進行了深入的研究,完成了UniPHY物理接口的設(shè)計;(4)搭建了軟硬件測試平臺,采用Modelsim和Quartus Ⅱ 12.1軟件對DDR3控制器的數(shù)據(jù)讀寫功能進行了系統(tǒng)的測試及驗證工作,切實保證了控制器的實際應(yīng)用價值和良好的穩(wěn)定性。
[Abstract]:Nowadays, with the rapid development of processor technology, the performance requirements of high-speed and large-capacity memory are becoming more and more stringent. Among the common random memory devices, DDR3 memory is the most widely used. DDR3 memory has many advantages, such as high speed, large capacity, low price and so on. Because the memory can not answer the memory access command of the processor directly, and the logic of operation is very complicated, the requirement of reading and writing timing is especially strict. Therefore, the design of a memory controller with good performance will be the focus of future efforts in this field. In addition, in recent years, the overall performance of FPGA is also increasing rapidly. The new generation of FPGA has been able to provide more logical resources, faster computing speed and richer memory interface solutions. Therefore, the choice of FPGA to assist the design of memory controller is favored by more and more developers. In this paper, DDR3 high speed and large capacity memory is taken as the research object. Combined with the development of memory at home and abroad, the characteristics and application principle of DDR3 memory chip are analyzed in detail. Finally, a DDR3 controller based on Altera Stratix 鈪，
本文編號：2341041
[Abstract]:Nowadays, with the rapid development of processor technology, the performance requirements of high-speed and large-capacity memory are becoming more and more stringent. Among the common random memory devices, DDR3 memory is the most widely used. DDR3 memory has many advantages, such as high speed, large capacity, low price and so on. Because the memory can not answer the memory access command of the processor directly, and the logic of operation is very complicated, the requirement of reading and writing timing is especially strict. Therefore, the design of a memory controller with good performance will be the focus of future efforts in this field. In addition, in recent years, the overall performance of FPGA is also increasing rapidly. The new generation of FPGA has been able to provide more logical resources, faster computing speed and richer memory interface solutions. Therefore, the choice of FPGA to assist the design of memory controller is favored by more and more developers. In this paper, DDR3 high speed and large capacity memory is taken as the research object. Combined with the development of memory at home and abroad, the characteristics and application principle of DDR3 memory chip are analyzed in detail. Finally, a DDR3 controller based on Altera Stratix 鈪，
本文編號：2341041
本文鏈接：http://sikaile.net/kejilunwen/jisuanjikexuelunwen/2341041.html
最近更新
教材專著
