【摘要】：XDNP網(wǎng)絡(luò)處理器是一個(gè)單片多處理器系統(tǒng)，內(nèi)部包含大量用于處理網(wǎng)絡(luò)協(xié)議的硬件模塊、多核多線程的調(diào)度模塊、以及總線仲裁模塊等。因此，在對(duì)網(wǎng)絡(luò)處理器功能驗(yàn)證的過程中，基于EDA工具的仿真手段效率低下，，驗(yàn)證時(shí)間冗長(zhǎng)。而FPGA原型驗(yàn)證通過搭建真實(shí)的應(yīng)用環(huán)境來(lái)驗(yàn)證芯片設(shè)計(jì)的正確性，克服了基于仿真器的系統(tǒng)級(jí)驗(yàn)證所具有的仿真速度慢、驗(yàn)證不全面等缺點(diǎn)，使得驗(yàn)證工作更加快速和全面。 基于以上目的，本文主要研究?jī)?nèi)容為XDNP網(wǎng)絡(luò)處理器的FPGA原型驗(yàn)證平臺(tái)設(shè)計(jì)。本文將硬件驗(yàn)證方案分為兩種：FPGA原型驗(yàn)證和MPE-BUS芯片驗(yàn)證。在FPGA原型驗(yàn)證方案中，XDNP全部功能由FPGA芯片實(shí)現(xiàn)；MPE-BUS芯片驗(yàn)證方案中，本課題組采用eASIC Nextreme90nm工藝將XDNP系統(tǒng)中最核心部分，即6個(gè)同構(gòu)包處理引擎PE及片上總線，進(jìn)行流片，得到MPE-BUS芯片，剩余功能采用FPGA實(shí)現(xiàn)。 本文提出了驗(yàn)證平臺(tái)的設(shè)計(jì)方案，完成了XDNP-DEMODOARD板的原理圖設(shè)計(jì)，并實(shí)現(xiàn)了該驗(yàn)證平臺(tái)的硬件設(shè)計(jì)。利用該驗(yàn)證平臺(tái)，基于Intel IXP1200系統(tǒng)附帶的L3fwd8_1f和L3fwd2f參考程序?qū)DNP系統(tǒng)完成了功能驗(yàn)證，其中L3fwd8_1f參考程序用于百兆對(duì)百兆路由功能的測(cè)試，L3fwd2f參考程序用于千兆對(duì)千兆路由功能的測(cè)試，驗(yàn)證結(jié)果表明FPGA原型和MPE-BUS芯片驗(yàn)證方案均能正確實(shí)現(xiàn)百兆口和百兆口之間以及千兆口和千兆口之間的IP層網(wǎng)絡(luò)通信。
[Abstract]:XDNP network processor is a monolithic multiprocessor system, which contains a large number of hardware modules used to process network protocols, multi-core multi-thread scheduling module, and bus arbitration module. Therefore, in the process of network processor function verification, the simulation method based on EDA tool is inefficient and the verification time is long. FPGA prototype verification verifies the correctness of chip design by building a real application environment, which overcomes the shortcomings of system level verification based on simulator, such as slow simulation speed and incomplete verification, which makes the verification work faster and more comprehensive. Based on the above purpose, this paper focuses on the design of FPGA prototype verification platform for XDNP network processor. In this paper, hardware verification schemes are divided into two types: FPGA prototype verification and MPE-BUS chip verification. In the FPGA prototype verification scheme, all the functions of XDNP are realized by FPGA chip. In the verification scheme of MPE-BUS chip, the core part of XDNP system, that is, six isomorphism packet processing engine PE and on-chip bus, is processed by eASIC Nextreme90nm technology, and the MPE-BUS chip is obtained. The remaining functions are realized by FPGA. In this paper, the design scheme of the verification platform is put forward, the schematic design of the XDNP-DEMODOARD board is completed, and the hardware design of the verification platform is realized. Based on the L3fwd8_1f and L3fwd2f reference programs attached to the Intel IXP1200 system, the XDNP system is verified by the platform, and the L3fwd8_1f reference program is used to test the 100-megabit routing function. L3fwd2f reference program is used to test gigabit to gigabit routing function. The results show that both FPGA prototype and MPE-BUS chip verification scheme can correctly realize IP layer network communication between 100m port and 100m port and between Gigabit port and gigabit port.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP332;TN791

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本文編號(hào)：2340942